• 제목/요약/키워드: Loop on time

검색결과 1,208건 처리시간 0.028초

A Study on the Pitch Search Time Reduction of G.723.1 Vocoder by Improved Hybrid Domain Cross-correlation (개선된 혼성영역 교차상관법에 의한 G.723.1의 피치검색시간 단축에 관한 연구)

  • Jo, Wang-Rae;Choi, Seong-Young;Bae, Myung-Jin
    • The Transactions of The Korean Institute of Electrical Engineers
    • /
    • 제59권12호
    • /
    • pp.2324-2328
    • /
    • 2010
  • In this paper we proposed a new algorithm that can reduce the open-loop pitch estimation time of G.723.1. The time domain cross-correlation method is simple but has long processing time by recursive multiplication. For reduction of processing time, we use the method that compute the cross-correlation by multiplying the Fourier value of speech by it's complex conjugate. Also, we can reduce the processing time by omitting the bit-reversing of FFT and IFFT for time-frequency domain transform. As a result, the processing time of improved hybrid domain cross-correlation algorithm is reduced by 67.37% of conventional time domain cross-correlation.

A New Synchronization Scheme for Parallel Processing of Loop with Constant and Variable Dependence Distance (불변 및 가변 종속거리를 갖는 루프의 병렬처리를 위한 새로운 동기화 기법)

  • 이광형;황종선;박두순
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • 제32B권5호
    • /
    • pp.693-701
    • /
    • 1995
  • In most application programs, loops usually comprise most of the computation in a program and are the most important source of parallelism. When loops are executed on multiprocessors, the cross iteration data dependences need to be enforced by synchronization between processors. Existing synchronization schemes have been studied mainly on the loop with constant dependence distance. When these schemes are applied to the loop with variable dependence distance, there exists lots of overhead by the use of unnecessary synchronization variables and execution of unuseful synchronization instructions. Even though there exist various variable synchronization schemes, they have a lot of run-time overhead to compute synchronization information. In this paper, we present a new synchronization scheme, Synch-Free/Synch-Hold for managing synchronization efficiently on the loop with constant and variable dependence distance.

  • PDF

Model Updating Using the Closed-loop Natural Frequency (폐루프 공진 주파수를 이용한 모델 개선법)

  • Jung Hunsang;Park Youngjin
    • Transactions of the Korean Society for Noise and Vibration Engineering
    • /
    • 제14권9호
    • /
    • pp.801-810
    • /
    • 2004
  • Parameter modification of a linear finite element model(FEM) based on modal sensitivity matrix is usually performed through an effort to match FEM modal data to experimental ones. However, there are cases where this method can't be applied successfully; lack of reliable modal data and ill-conditioning of the modal sensitivity matrix constitute such cases. In this research, a novel concept of introducing feedback loops to the conventional modal test setup is proposed. This method uses closed-loop natural frequency data for parameter modification to overcome the problems associated with the conventional method based on modal sensitivity matrix. We proposed the whole procedure of parameter modification using the closed-loop natural frequency data including the modal sensitivity modification and controller design method. Proposed controller design method is efficient in changing modes. Numerical simulation of parameter estimation based on time-domain input/output data is provided to demonstrate the estimation performance of the proposed method.

Observer-Based Adaptive Guidance Law Considering Target Uncertainties and Control Loop Dynamics (목표물의 불확실성과 제어루프 특성을 고려한 추정기 기반 적응 유도기법)

  • 최진영;좌동경
    • Journal of Institute of Control, Robotics and Systems
    • /
    • 제10권8호
    • /
    • pp.680-688
    • /
    • 2004
  • This paper proposes an observer-based method for adaptive nonlinear guidance. Previously, adaptive nonlinear guidance law is proposed considering target maneuver and control loop dynamics. However, several information of this guidance law is not available, and therefore needs to be estimated for more practical application. Accordingly, considering the unavailable information as bounded time-varying uncertainties, an integrated guidance and control model is re-formulated in normal form with respect to available states including target uncertainties and control loop dynamics. Then, a nonlinear observer is designed based on the integrated guidance and control model. Finally, using the estimates for states and uncertainties, an observer-based adaptive guidance law is proposed to guarantee the desired interception performance against maneuvering target. The proposed approach can be effectively used against target maneuver and the limited performance of control loop. The stability analyses and simulations of the proposed observer and guidance law are included to demonstrate the practical application of our scheme.

Time Delay Control of Noncolocated Flexible System in z-Domain (비병치 유연계의 시간지연 이산제어)

  • 강민식
    • Transactions of the Korean Society of Mechanical Engineers
    • /
    • 제16권6호
    • /
    • pp.1089-1098
    • /
    • 1992
  • This paper concerns a discrete time control of noncolocated flexible mechanical systems by using time delay relation. A stability criterion of closed-loop system is derived in discrete time domain and a graphic method is developed for designing controllers. Based on this method, a derivative controller is designed for a simply supported uniform beam in the cases of colocation without time delay and of noncolocation with time delay. Some simulation results show the effectiveness of the suggested control.

A Study on the Development of HWIL Simulation Control System for High Maneuver Guided Missile System (고기동 유도무기를 위한 HWIL 시뮬레이션 제어 시스템 개발 연구)

  • Kim, Woon-Sik;Lee, Byung-Sun;Kim, Sang-Ha
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • 제35권11B호
    • /
    • pp.1659-1666
    • /
    • 2010
  • The High maneuver missiles use various interfaces and high speed guidance and control loop. Hardware-in-the-Loop(HWIL) simulation control system, therefore, should have high performance computing power and hardware interface capabilities, and should be developed using IT technology with which real time operating system, embedded system, data communication technology, and real time hardware control are integrated. This paper suggests the control system design techniques, such as a system hardware configuration, a job distribution algorithm for high performance multi-processors, a real time calculation and control mechanism, inter-processor communication mechanism, and a real time data acquisition technique, to perform the HWIL simulation for high maneuver missile system.

A Study on Closed-Loop Control of a Stepping Motor for Resonance Elimination (공진배제를 위한 스템핑 모터의 폐회로제어에 관한 연구)

  • 노상현;김교형
    • Transactions of the Korean Society of Mechanical Engineers
    • /
    • 제15권1호
    • /
    • pp.90-97
    • /
    • 1991
  • A stepping motor can be driven with open-loop or closed-loop control. The major disadvantage of open-loop control is that it is subjected to resonance and instability in certain speed range, and that there is no way to check stalling or error in position. In this paper, a closed-loop control system consisting of a microcomputer, a hybrid stepping motor, a drive, a lead screw, and an encoder which is used as a position sensor is developed. A control program is programmed in assembly language for real time control and the versatile interface adapter(VIA) is used as the interface with the microcomputer. The experimental results of the stepping motor were eliminated on all kinds of inertia load, and maximum start stop pulse rate and maximum slewing pulse rate were also increased about twice respectively.

Direct Digital Control of Single-Phase AC/DC PWM Converter System

  • Kim, Young-Chol;Jin, Lihua;Lee, Jin-Mok;Choi, Jae-Ho
    • Journal of Power Electronics
    • /
    • 제10권5호
    • /
    • pp.518-527
    • /
    • 2010
  • This paper presents a new technique for directly designing a linear digital controller for a single-phase pulse width modulation (PWM) converter systems, based on closed-loop identification. The design procedure consists of three steps. First, obtain a digital current controller for the inner loop system by using the error space approach, so that the power factor of the supply is close to one. The outer loop is composed of a voltage controller, a current control loop including a current controller, a PWM converter, and a capacitor. Then, all the components, except the voltage controller, are identified by a discrete-time equivalent linear model, using the closed-loop output error (CLOE) method. Based on this equivalent model, a proper digital voltage controller is then directly designed. It is shown through PSim simulations and experimental results that the proposed method is useful for the practical design of PWM converter controllers.

The Parallelism Extraction in Loops with Procedure Calls (프로시저 호출을 가진 루프에서 병렬성 추출)

  • 장유숙;박두순
    • Journal of Korea Multimedia Society
    • /
    • 제4권3호
    • /
    • pp.270-279
    • /
    • 2001
  • Since most program execution time is spent in the loop structure, extracting parallelism from sequential loop programs hale been focused. But, most programs hare implicit parallelism of interprocedure. This paper presents a generalized Parallelism extraction in loop\ulcorner with procedure calls. Most parallelization of loops with Procedure calls just focus on the uniform code which data dependency distance is constant. We presents algorithms which can be applied with uniform code, nonuniform code, and complex code. The proposed algorithm, loop extraction, loop embedding and procedure cloning transformation methods evaluate using CRAY-T3E. The result of performance evaluation is that proposed algorithm is an effect.

  • PDF

A Fast Locking Dual-Loop PLL with Adaptive Bandwidth Scheme (루프 대역폭 조절기를 이용한 빠른 위상 고정 시간을 갖는 이중 루프 위상고정루프)

  • Song, Youn-Gui;Choi, Young-Shig
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • 제45권5호
    • /
    • pp.65-70
    • /
    • 2008
  • A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.