• Journal of Power Electronics
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• v.7 no.4
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• pp.310-317
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• 2007

In this paper, an analysis and hysteretic controller design of a $3^{rd}$ order buck converter is presented. The proposed hysteretic controller consists of an inner current-loop, just like the conventional cascade control scheme, and an outer voltage-loop for load voltage regulation. Although it is possible to include an inner current loop from different branches of the converter, from the feasibility and operational point of view, the load side capacitor current would be the better choice. The addition of an inner current-loop improves the dynamic performance of the converter while preserving the robustness of the hysteretic control. The controller formulation and closed-loop converter performance analysis are validated through computer simulations. Few experimental results of the proposed converter are given and compared with the buck converter.

• Journal of Broadcast Engineering
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• v.18 no.2
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• pp.261-270
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• 2013

A stereoscopic 3D video service is able to provide a 3D video service while keeping backward compatibility with the existing 2D video service. In the terrestrial digital television (DTV) system, a stereoscopic video codec is required to have high coding efficiency in order to provide a 3D video service in the same channel capacity. A hybrid codec consisting of MPEG-2 for base video and H.264/AVC or HEVC for 3D auxiliary video is considered. Furthermore, Non-Real-Time (NRT) delivery of stereoscopic video is also considered as a service scenario for 3DTV services to overcome the limited bandwidth. In this paper, we propose a stereoscopic video coding scheme using adaptive loop filter (ALF) which had been considered in HEVC as a pre-/post-filter for enhancing coding efficiency in NRT-based 3DTV services. In order to apply ALF as a post-filter to the reconstructed additional view coded by H.264/AVC, we devise a method in which ALF is adaptively applied based on a structure determined by using macroblock (MB) coding information such as MB mode type and reference index instead of coding unit (CU) structure on which ALF is applied in the HEVC. Experimental results shows that the proposed stereoscopic video coding scheme applying ALF obtains up to 24.9% gain of bit saving.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.295-298
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• 2014

In this paper, an efficient design of HEVC Adaptive Loop Filter(ALF) for filter coefficients estimation is proposed. The ALF performs Cholesky decomposition of $10{\times}10$ matrix iteratively to estimate filter coefficients. The Cholesky decomposition of the ALF consists of root and division operation which is difficult to implement in a hardware design because it needs to many computation rate and processing time due to floating-point unit operation of large values of the Maximum 30bit in a LCU($64{\times}64$). The proposed hardware architecture is implemented by designing a root operation based on Cholesky decomposition by using multiplexer, subtracter and comparator. In addition, The proposed hardware architecture of efficient and low computation rate is implemented by designing a pipeline architecture using characteristic operation steps of Cholesky decomposition. An implemented hardware is designed using Xilinx ISE 14.3 Vertex-6 XC6VCX240T FPGA device and can support a frame rate of 40 4K Ultra HD($4096{\times}2160$) frames per second at maximum operation frequency 150MHz.

• Journal of Power Electronics
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• v.16 no.4
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• pp.1565-1577
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• 2016

For grid-connected LCL-filtered inverters, dual-loop current control with an inner-loop active damping (AD) based on capacitor current feedback is generally used for the sake of current quality. However, existing studies on capacitor current feedback AD with a control delay do not reveal the mathematical relation among the dual-loop stability, capacitor current feedback factor, delay time and LCL parameters. The robustness was not investigated through mathematical derivations. Thus, this paper aims to provide a systematic study of dual-loop current control in a digitally-controlled inverter. At first, the stable region of the inner-loop AD is derived. Then, the dual-loop stability and robustness are analyzed by mathematical derivations when the inner-loop AD is stable and unstable. Robust design principles for the inner-loop AD feedback factor and the outer-loop current controller are derived. Most importantly, ensuring the stability of the inner-loop AD is critical for achieving high robustness against a large grid impedance. Then, several improved approaches are proposed and synthesized. The limitations and benefits of all of the approaches are identified to help engineers apply capacitor current feedback AD in practice.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.4
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• pp.41-49
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• 2008

H.264/AVC supports variable block motion compensation, multiple reference images, 1/4-pixel motion vector accuracy, and in-loop deblocking filter, compared with the existing compression technologies. While these coding technologies are major functions of compression rate improvement, they lead to high complexity at the same time. For the H.264 video coding technology to be actually applied on low-end / low-bit rates terminals more extensively, it is essential to improve tile coding speed. Currently the deblocking filter that can improve the moving picture's subjective image quality to a certain degree is used on low-end terminals to a limited extent due to computational complexity. In this paper, a performance improvement method of the deblocking filter that efficiently reduces the blocking artifacts occurred during the compression of low-bit rates digital motion pictures is suggested. In the method proposed in this paper, the image's spatial correlational characteristics are extracted by using the variable block information of motion compensation; the filtering is divided into 4 modes according to the characteristics, and adaptive filtering is executed in the divided regions. The proposed deblocking method reduces the blocking artifacts, prevents excessive blurring effects, and improves the performance about $30{\sim}40%$ compared with the existing method.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 2000.04b
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• pp.365-370
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• 2000

A sliding mode fuzzy control (SMFC) algorithm is applied to design a controller for a benchmark problem on a wind- excited building. The structure is a 76-story concrete office tower with a height of 306 meters, hence the wind resistance characteristics are very important for the serviceability as well as the safety. A control system with an active tuned mass damper is assumed to be installed on the top floor. Since the structural acceleration is measured only at ,limited number of locations without measurement of the wind force, the structure of the conventional continuous sliding mode control may have the feed-back loop only. So, an adaptive least mean squares (LMS) filter is employed in the SMFC algorithm to generate a fictitious feed-forward loop. The adaptive LMS filter is designed based on the information of the stochastic characteristics of the wind velocity along the structure. A numerical study is carried out. and the performance of the present SMFC with the ,adaptive LMS filter is investigated in comparison with those of' other control, of algorithms such as linear quadratic Gaussian control, frequency domain optimal control, quadratic stability control, continuous sliding mode control, and H/sub ∞///sub μ/, control, which were reported by other researchers. The effectiveness of the adaptive LMS filter is also examined. The results indicate that the present algorithm is very efficient .

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.12
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• pp.6022-6026
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• 2012

This article presents a band-stop filter (BSF) by using a periodic structure property of frequency selective surfaces (FSSs) embedded in a microstrip transmission line. The proposed BSF is designed with FSS unit cells modifying the cross-loop slots. The BSF is interpreted with an equivalent circuit model and a dispersion diagram. The center frequency (fo) of the BSF is 6.6GHz. Proposed filter increases the number of unit cell. As a result, 3dB bandwidth is wider and insertion loss is reduced. Also, Facbricated BSF exhibits uniplanar geometry, simple fabrication.

• Journal of Astronomy and Space Sciences
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• v.14 no.2
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• pp.386-394
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• 1997

In this study, a few of the modeling methods for flexible spacecraft were introduced and adopted to the modeling of a 3-axes stabilization satellite. The generated model was put into pre-built rigid body attitude control loop. A Lumped Parameter Model(Global Mode Model: GMM) was recommended for the absence of the Finite Element Method(FEM) model. Finally, GMM was compared with FEM in terms of designing a control filter. A 1st-order filter was designed to meet requirements of the controller since the new flexible model was applied, and that filter was added to motor controller and axis controller. MATLAB/Simulink was used as a tool for design and simulation of the control loop and filter.

• Nuclear Engineering and Technology
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• v.54 no.6
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• pp.2011-2022
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• 2022

According to the defense-in-depth concept, not only a preventive strategy but also an integrated cyberattack response strategy for NPPs should be established. However, there are limitations in terms of responding to penetrations, and the existing EOPs are insufficient for responding to intentional disruptions. In this study, we focus on manipulative attacks on process data. Based on an analysis of the related attack vectors and possible attack scenarios, we adopt the Kalman filter to detect process anomalies that can be caused by manipulations of process data. To compensate for these manipulations and secure MCR operators' situational awareness, we modify the Kalman filter such that it can filter out the effects of the manipulations adaptively. A case study was conducted using a hardware-in-the-loop system. The results indicated that the developed method can be used to verify whether the displayed safety-related state data are reliable and to implement the required safety response actions.