• KSII Transactions on Internet and Information Systems (TIIS)
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• v.3 no.1
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• pp.5-25
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• 2009

In recent years the popularity of multi-hop wireless networks has been growing. Its flexible topology and abundant routing path enables many types of applications. However, the lack of a centralized controller often makes it difficult to design a reliable service in multi-hop wireless networks. While packet routing has been the center of attention for decades, recent research focuses on data discovery such as file sharing in multi-hop wireless networks. Although there are many peer-to-peer lookup (P2P-lookup) schemes for wired networks, they have inherent limitations for multi-hop wireless networks. First, a wired P2P-lookup builds a search structure on the overlay network and disregards the underlying topology. Second, the performance guarantee often relies on specific topology models such as random graphs, which do not apply to multi-hop wireless networks. Past studies on wireless P2P-lookup either combined existing solutions with known routing algorithms or proposed tree-based routing, which is prone to traffic congestion. In this paper, we present two wireless P2P-lookup schemes that strictly build a topology-dependent structure. We first propose the Ring Interval Graph Search (RIGS) that constructs a DHT only through direct connections between the nodes. We then propose the ValleyWalk, a loosely-structured scheme that requires simple local hints for query routing. Packet-level simulations showed that RIGS can find the target with near-shortest search length and ValleyWalk can find the target with near-shortest search length when there is at least 5% object replication. We also provide an analytic bound on the search length of ValleyWalk.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3B
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• pp.65-71
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• 2005

The primary function of the Internet routers is to forward incoming packets toward their final destinations. IP address lookup is one of the most important functions in evaluating router performance since IP address lookup should be performed in wire-speed for the hundred-millions of incoming packets per second. With CIDR, the IP prefixes of routing table have arbitrary lengths, and hence address lookup by exact match is no longer valid. As a result, when packets arrive, routers compare the destination IP addresses of input packets with all prefixes in its routing table and determine the most specific entry among matching entries, and this is called the longest prefix matching. In this paper, based on parallel multiple hashing and prefix grouping, we have proposed a hardware architecture which performs an address lookup with a single memory access.

• Journal of KIISE:Information Networking
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• v.32 no.3
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• pp.427-432
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• 2005

Packet arrival rates in internet routers have been dramatically increased due to the advance of link technologies, and hence wire-speed packet processing in Internet routers becomes more challenging. As IP address lookup is one of the most essential functions for packet processing, algorithm and architectures for efficient IP address lookup have been widely studied. In this paper, we Propose an efficient I address lookup architecture which shows yeW good Performance in search speed while requires a single small-size memory The proposed architecture is based on multi-way tree structure which performs comparisons of multiple prefixes by one memory access. Performance evaluation results show that the proposed architecture requires a 280kByte SRAM to store about 40000 prefix samples and an address lookup is achieved by 5.9 memory accesses in average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• Journal of KIISE:Databases
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• v.36 no.2
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• pp.84-98
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• 2009

Various algorithms and architectures for IP address lookup have been studied to improve forwarding performance in the Internet routers. Previous IP address lookup architecture using Bloom filter requires a separate Bloom filter as well as a separate hash table in each prefix length, and hence it is not efficient in implementation complexity. To reduce the number of hash tables, it applies controlled prefix expansion, but prefix duplication is inevitable in the controlled prefix expansion. Previous parallel multiple-hashing architecture shows very good search performance since it performs parallel search on tables constructed in each prefix length. However, it also has high implementation complexity because of the parallel search structure. In this paper, we propose a new IP address lookup architecture using all-length Bloom filter and all-length multiple hash table, in which various length prefixes are accomodated in a single Bloom filter and a single multiple hash table. Hence the proposed architecture is very good in terms of implementation complexity as well as search performance. Simulation results using actual backbone routing tables which have $15000{\sim}220000$ prefixes show that the proposed architecture requires 1.04-1.17 memory accesses in average for an IP address lookup.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.46.1-46
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• 2002

$\textbullet$ Abstract $\textbullet$ Introduction $\textbullet$ Liquid Level Control System $\textbullet$ Flow Ratio Control System $\textbullet$ Application of Lookup Table Technique $\textbullet$ Experimental Results $\textbullet$ Conclusion

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.3
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• pp.873-889
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• 2014

IP address lookup is very crucial in performance of routers. Several works have been done on prefix caching to enhance the performance of IP address lookup. Since a prefix represents a range of IP addresses, a prefix cache shows better performance than an IP address cache. However, not every prefix is cacheable in itself. In a prefix cache it causes false hit to cache a non-leaf prefix because there is possibly the longer matching prefix in the routing table. Prefix expansion techniques such as complete prefix tree expansion (CPTE) make it possible to cache the non-leaf prefixes as the expanded forms, but it is hard to manage the expanded prefixes. The expanded prefixes sometimes incur a great deal of update overhead in a routing table. We propose a bitmap-based prefix cache (BMCache) to provide low update overhead as well as low cache miss ratio. The proposed scheme does not have any expanded prefixes in the routing table, but it can expand a non-leaf prefix using a bitmap on caching time. The trace-driven simulation shows that BMCache has very low miss ratio in spite of its low update overhead compared to other schemes.

• Journal of the Korea Society of Computer and Information
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• v.20 no.12
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• pp.45-52
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• 2015

We propose a hybrid prefix caching scheme to enable high speed IP address lookup. All prefixes loaded in a prefix cache should not be overlapped in address range for correct IP lookup. So, every non-leaf prefix needs to be expanded not so as to be overlapped. The shorter expanded prefix is more preferable because it can cover wider address range just as an single entry in a prefix cache. We exploits advantages of two dynamic prefix expansion techniques, bounded prefix expansion technique and bitmap-based prefix expansion technique. The proposed scheme uses dual bound values whereas just one bound value is used in bounded prefix expansion. Our elaborated technique make the dual bound values be associated with several subtries flexibly using bitmap information, rather than with fixed subtries. We evaluate the performance of the proposed scheme in terms of the average length of the expanded prefixes and cache miss ratio. The experiment results show the proposed scheme has lower cache miss ratio than other previous schemes including both bounded prefix expansion and bitmap-based expansion irrespective of the cache size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1642-1651
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• 2004

Advance of internet access technology requires more internet bandwidth and high-speed packet processing. IP address lookups in routers are essential elements which should be performed in real time for packets arriving tens-of-million packets per second. In this paper, we proposed a new architecture for efficient IP address lookup. The proposed scheme produces multiple balanced trees stored into a single SRAM. The proposed scheme performs sequential binary searches on multiple trees. Performance evaluation results show that p개posed architecture requires 301.7KByte SRAM to store about 40,000 prefix samples, and an address lookup is achieved by 11.3 memory accesses in average.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1B
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• pp.18-28
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• 2004

Efficient hardware implementation of address lookup is one of the most important design issues of internet routers. Address lookup significantly impacts router performance since routers need to process tens-to-hundred millions of packets per second in real time. In this paper, we propose a practical IP address lookup structure based on the binary tree of prefixes of different lengths. The proposed structure produces multiple balanced trees, and hence it solve the issues due to the unbalanced binary prefix tree of the existing scheme. The proposed structure is implemented using pipelined binary search combined with a small size TCAM. Performance evaluation results show that the proposed architecture requires a 2000-entry TCAM and total 245 kbyte SRAMs to store about 30,000 prefix samples from MAE-WEST router, and an address lookup is achieved by a single memory access. The proposed scheme scales very well with both of large databases and longer addresses as in IPv6.