• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.895-898
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• 2005

This paper describes a design of LNS-based divider and square-root circuits which are key arithmetic units in graphic processor and digital signal processor. To achive area-efficient and low-power that is an essential consideration for mobile environment, a fixed-point format of 16.16 is adopted instead of conventional floating-point format. The designed divider and square-root units consist of binary-to-logarithm converter, subtractor, logarithm-to-binary converter. The binary to logarithm converter is designed using combinational logic based on six regions approximation method. As a result, gate count reduction is obtained when compared with conventional lookup approack. The designed units is 3,130 gate count and 1,280 gate count. To minimize average percent error 3.8% and 4.2%. error compensation method is employed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2633-2640
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• 2009

We design a small-area, low-power, and high-speed EEPROM for touch screen controller IC. As a small-area EEPROM design, a SSTC (side-wall selective transistor) cell is proposed, and high-voltage switching circuits repeated in the EEPROM core circuit are optimized. A digital data-bus sensing amplifier circuit is proposed as a low-power technology. For high speed, the distributed data-bus scheme is applied, and the driving voltage for both the EEPROM cell and the high-voltage switching circuits uses VDDP (=3.3V) which is higher than the logic voltage, VDD (=1.8V), using a dual power supply. The layout size of the designed 128-KBit EEPROMIP is $662.31{\mu}m{\times}1314.89{\mu}m$.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
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• v.7 no.2
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• pp.227-236
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• 2017

Quantum-dot cellular automata(QCA) consists of nano-scale cells and demands very low power consumption so that it is one of the alternative technologies that can overcome the limits of scaling CMOS technologies. Various circuits on QCA have been researched until these days, a latch required for counter and state control has been proposed as a component of sequential logic circuits. A latch uses a feedback loop to maintain previous state. In QCA, a latch uses a square structure using 4 clocks for feedback loop. Previous latches have been proposed using many cells and clocks in coplanar. In this paper, in order to eliminate these defects, we propose a SR and D latch using multilayer structure on QCA. Proposed three dimensional loop structure is based on multilayer and consists of 3 layers. Each layer has 2 clock differences between layers in order to reduce interference. The proposed latches are analyzed and compared to previous designs.

• Advances in Energy Research
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• v.7 no.1
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• pp.1-19
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• 2020

Energy consumption of air-conditioning and refrigeration systems is responsible for about 25 to 30% of the energy demand especially in hot seasons. This equipment is mostly electricity dependent and their use in principle affects negatively the environment. Enhancing the energy efficiency of the existing equipment is important as one of the measures to reduce environment impacts. This paper reports the results of an experimental study to evaluate the impacts of the use electronic expansion valve and variable velocity compressor on the performance of vapor compression refrigeration system. The experimental rig is composed of two independent circuits one for the vapor compression system and the other is the secondary fluid system. The vapor compression system is composed of a forced air condenser unit, evaporator, hermetic compressor and expansion elements, while the secondary system has a pump for circulating the secondary fluid, and an air conditioning heat exchanger. The manufacturer's data was used to determine the optimal points of operation of the system and consequently tests were done to evaluate the influence of variation of the compressor velocity and the opening of the expansion device on the performance of the refrigeration system. A fuzzy logic model was developed to control the rotational velocity of the compressor and the thermal load. Fuzzy control model was made in LabVIEW software with the objective of improving the system performance, stability and energy saving. The results showed that the use of fuzzy logic as a form of control strategy resulted in a better energy efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.4
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• pp.617-622
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• 2018

In industries such as automobiles and semiconductors, a lot of components are produced using PLCs based on an automatic production system. Therefore, an educational platform is needed to provide training in the use of PLCs in the industrial sites. Conventional educational systems, in which PLCs are employed to control sensors and actuators, have been continuously developed. However, these systems present their circuits only in 2D on the screen, which makes it difficult to understand them during the learning process. To overcome these disadvantages, we propose an educational V-Factory system capable of providing PLC training using virtual reality. In addition, thousands of sensors and actuators can be controlled by the V-Factory system through the proposed virtual I/O driver. The motion of the automatic production system can be visualized using virtual reality.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.6
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• pp.9-17
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• 1999

In this paper, we propose a new technology mapping algorithm for CPLD under time constraint. In our technology mapping algorithm, a given logic equation is constructed as the DAG type, then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs to be minimized. Also, after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within CLB. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces delay time and the number of CLBs much more than the existing tools of technology mapping algoritm.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.29-36
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• 2016

Recently a new class of quantum gate called $NCV-{\mid}v_1$ > library with low cost realizable potentialities is being watched with keen interest. The $NCV-{\mid}v_1$ > MCT gate is composed of AND cascaded-$CV-{\mid}v_1$ > gates to control the target qudit and its adjoint gates to erase junk ones. This paper presents a new symmetrical duality library named $NCV^{\dag}-{\mid}v_1$ > library corresponding to $NCV-{\mid}v_1$ > library. The new $NCV^{\dag}-{\mid}v_1$ > library can be operated on OR logic under certain conditions. By using both the $NCV-{\mid}v_1$ > and $NCV^{\dag}-{\mid}v_1$ > libraries it is possible to realize MPMCT gates, SOP and POS type synthesis of quantum logic circuits with extremely low cost, and expect dual gate property caused by different operational attributes with respect to forward and backward operations.

• Journal of Advanced Navigation Technology
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• v.14 no.5
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• pp.710-717
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• 2010

Even though there are 256 possible 1-qudit(1-variable quantum digit) functions in quaternary logic, the most useful functions are 4!=24 ones capable of representing in QGFSOP expressions by possible permuting of 0,1,2, and 3. In this paper, we propose a permutational literal(PL) representation and a QPL(Quaternary PL) gate which use the operands of a multiplicand A and an augend D in $Ax^C$+D(GF4) operation as a control variable of multi-cascaded PLs. And we also present new PL synthesis algorithms to synthesize QGFSOP expressed 24 (1-qudit) functions by applying three PL operators as ab(mutual permutation), + D(addition), and XA (multiplication). Finally architectures, circuits, and a CMOS implementation to realize proposed PL synthesis algorithms for $Ax^C$+D(GF4) functions are presented.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.5
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• pp.857-864
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• 2006

This paper describes a design of low-power/small-area arithmetic circuits which are vector processing unit powering nit, divider unit and square-root unit for mobile 3D graphic accelerator. To achieve area-efficient and low-power implementation that is an essential consideration for mobile environment, the fixed-point f[mat of 16.16 is adopted instead of conventional floating-point format. The vector processing unit is designed using redundant binary(RB) arithmetic. As a result, it can operate 30% faster and obtained gate count reduction of 10%, compared to the conventional methods which consist of four multipliers and three adders. The powering nit, divider unit and square-root nit are based on logarithm number system. The binary-to-logarithm converter is designed using combinational logic based on six-region approximation method. So, the powering mit, divider unit and square-root unit reduce gate count when compared with lookup table implementation.

• Journal of the Korea Society of Computer and Information
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• v.4 no.3
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• pp.35-46
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• 1999

In this paper, we propose a new CPLD technology mapping algorithm improving run-time under time constraint. In our technology mapping algorithm. a given logic equation is constructed as the DAG type. then the DAG is reconstructed by replicating the node that outdegree is more than or equal to 2. As a result, it makes delay time and the number of CLBs, run-time to be minimized. Also. after the number of multi-level is defined and cost of each nodes is calculated, the graph is partitioned in order to fit to k that is the number of OR term within Cl.B. The partitioned nodes are merged through collapsing and bin packing is performed in order to fit to the number of OR term within CLB. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces run-time much more than the TMCPLD.