• 한국정보통신학회논문지
• /
• 제10권7호
• /
• pp.1259-1265
• /
• 2006

본 논문에서는 고속 FPGA 설계를 위한 논리 수준의 조합회로 합성 알고리듬을 제안한다. 제안된 알고리듬은 회로의 지연시간을 줄이기 위해 critical path를 분할한다. 그리고 분할된 회로를 동시에 수행하는 구조를 갖는 회로를 생성한다. 본 커널 선택 알고리듬은 SUN UNIX 환경에서 C 언어로 구현되었다. 제안된 커널 선택 알고리듬은 기존의 FlowMap 지연시간 최적화 알고리듬과 결과를 비교하였다. 제안된 지연시간 최적화 알고리듬이 기존 알고리듬 에 비해 지연시간이 평균 33.3 % 감소된 회로를 생성함을 보였다.

• 정보과학회지
• /
• 제3권2호
• /
• pp.18-23
• /
• 1985

N値演算回路를 實現하기 爲해 基本函數로 多値論理和, 論理 積 및 Xabc를 定하여 多値多變數 Switching函數를 展開하였다. 이 Switching 函數의 簡單化에 對하여 생각하였으며 N値演算回路의 實現을 容易하게 하기 위하여 現在 使用되 고 있는 2値論理回路素子 및 2値 Etclusive-OR 論理를 應用할 수 있도록 Switching函數를 展開하였다. N値多變數演算回路로써 4値全加算器 및 半加算機를 一例로하여 論理式을 세웠다. 또, 2値論理系와 倂用할 수 있는 BCD 入力 10値全 加算器의 論理式을 展開하였다.

• Transactions on Electrical and Electronic Materials
• /
• 제7권5호
• /
• pp.240-246
• /
• 2006

The mathematical model of the power substation is proposed. The substation esteems as a set of the equipment elements which integrated common connections and electromagnetic field. Some capabilities of model represented by both electric networks and a discrete logical model demonstrated by non-directional graph. The model can be useful for solution of the problem of diagnostic of the high-voltage equipment.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
• /
• pp.221-225
• /
• 2000

We designed asynchronous event logic library with 0.25$\mu\textrm{m}$ CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6㎓. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about 1.1mm ${\times}$ 1.1mm.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.655-658
• /
• 2005

Due to reduced device sizes and threshold voltages, leakage current becomes an important issue in CMOS design. In a CMOS combinational logic circuit, the leakage current in the standby state depends on the state of the inputs and thus can be minimized by applying an optimal input when the circuit is idling. In this paper, we present a New Input Vector Control algorithm, called Leakage Minimization by Input vector Control (LMIC) for minimal leakage power. This algorithm finds the minimal leakage vector and reduces leakage current up to 22.% on the average, for TSMC 0.18um process parameters. Minimal leakage vectors are very useful in reducing leakage currents in standby mode of operation.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2005년도 추계종합학술대회
• /
• pp.865-868
• /
• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess

• 전기전자학회논문지
• /
• 제8권2호
• /
• pp.161-165
• /
• 2004

본 논문은 CMOS 에지 완료검출 신호를 이용하여 8bit 웨이브파이프라인 덧셈기를 설게하였다. 이 구조는 클럭이 필요 없이 동작한다. 에지감지후 신호완료를 검출하는 알고리즘회로는 센서회로와 래치로 구성되어있다. 제안하는 구조를 이용하여 8bit 덧셈기의 출력이 거의 같은 시간에 만들어 지도록 정렬된다. 시뮬레이션에서 0.35um CMOS 공정을 사용하여 3.3V 공급전압으로 1GHz 동작을 확인하였다.

• 전자공학회논문지B
• /
• 제33B권3호
• /
• pp.17-27
• /
• 1996

More fuzzy hardware are expected to be utilized in the future to construct fuzzy logic controllers (FLCs). It is hard to find an existing fuzzy hardware which is adopting advanced functions such as self-tuning algorithm in addition to the conventional inference calculation. That is mainly because conventional self-tuning algorithms designed to implement with some hardware circuits is required for fuzzy hardwares to have self-tuning capability. As a first step toward the feature, a novel self-tuning algorithm is proposed in this paper. Based on the search method, the main idea of the proposed algorithm is to detemine valid ranges of input variables of an FLC in order to maximize performance indices fo the control system. The performance indices are so ismple as to be realized by hardware circuit. in dadditon to the conventional scaling-factor adjustment, the algorithm adjusts offset values as well, which, in effect, modifies fuzzy rules of the FLC. To justify the performance of the proposed algorithm, a simulation study is executed.

• IEIE Transactions on Smart Processing and Computing
• /
• 제4권5호
• /
• pp.366-370
• /
• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• 한국음향학회지
• /
• 제18권1호
• /
• pp.45-52
• /
• 1999

본 논문에서는 HDTV 비디오 신호를 처리함에 있어 신호의 병목현상을 없애주고 신호의 원활한 처리를 위해 새로운 알고리듬을 적용하여 54MHz의 동작 주파수를 갖는 패커를 제안하고 설계하였다. 또한 제안된 패커의 성능을 검증하기 위해 조합논리를 이용한 ROM 테이블 구조를 갖는 DCT 계수 부호화부를 함께 설계하므로써 DCT 계수 부호화부의 출력을 제안된 패커의 입력 데이타로 사용하였다. 본 논문의 회로는 VHDL 코드를 이용하였고 SYNOPSYS tool의 $0.65{\mu}m$ 공정을 이용한 모델링과 시뮬레이션을 수행하였다.