• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.42-45
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• 1986

This paper introduces novel functionally integrated logic elements which are conceptuallized for large scale integrated circuits. Efforts are made to minimize the gate size as well as to reduce the operational voltage, without sacrificing the speed performance of the gates. The process used was a rather conventional collector diffusion isolation(CDI) process. New gate structures are formed by merging several transistors of a gate in the silicon substrate. Thested elements are CML(Current Mode Logic) and EECL (Emitter-to-Emitter Coupled Logic)gates. The obtained experimental results are power-delay product of 6~11pJ and delay time/gate of 1.6~1.8 ns, confirming the possibility of these novel gate structures as a VLSI-candidate.

• The Magazine of the IEIE
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• v.37 no.8
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• pp.50-59
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• 2010

$0.18-{\mu}m$ high voltage technology 13.5V high voltage well-based symmetric EDMOS isolated by MTI was designed and fabricated. Using calibrated process and device model parameters, the characteristics of the symmetric and asymmetric EDMOS have been simulated. The asymmetric EDMOS has higher performance, better $R_{sp}$ / BVDSS figure-of-merit, short-channel immunity and smaller pitch size than the symmetric EDMOS. The asymmetric EDMOST is a good candidate for low-power and smaller source driver chips. The low voltage logic well-based EDMOS process has advantages over high voltage well-based EDMOS in process cost by eliminating the process steps of high-voltage well/drift implant, high-temperature long-time thermal steps, etc. The specific on-resistance of our well-designed logic well-based EDMOSTs is compatible with the smallest one published. TCAD simulation and measurement results show that the improved logic well-based nEDMOS has better electrical characteristics than those of the conventional one. The improved EDMOS proposed in this paper is an excellent candidate to be integrated with low voltage logic devices for high-performance low-power low-cost chips.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.76-85
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• 1993

This paper describes the design of a technology-independent logic, function, and timing extraction system from SPICE-like network descriptions. Technology-independent extraction mechanism is provided in the form of technology files containing the rules for constructing logic gates and functional blocks. The designed system can be more effectively used in cell-based design by describing the cells to be extracted. Timing extraction is performed by using a linear RC gate delay model which takes interconnection delay into account. Experimental results show that estimated delay is within 10 percents for logic gate circuits when compared with SPICE. Through higher-level design descriptions obtained by extraction, design cycles can be considerably reduces.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2978-2990
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• 1996

With the advent of multimedia era, there are ever increasing interest in computer music and sound syntheis. An FM type sound synthesizing method makes possible the syntheis ofvarious sounds ofmusical instruments with a relatively simple hardware architecture. Therefore, in this paper, we designed a hardware architecture for real-time sound synthesizer and its logic gates. In this paper, we designed a basic sound generator for implementation of real-time logic gates, analzed characteristics of sounds synthesized in this architecture and extracted parameters of FM sounds of musical instruments by using the Csound software. The major bolkcs to build the hardware are a phase-generator, a singe-function-generator, an envelope-generator and a multiplier-part. Finally, logic circuits are designed and verified in VHDL and logic gates by 1.0um standard cell library, which will be easily implementable by the form of ASIC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.664-670
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• 2015

A four-times-VDD switch that supports high and low voltage mode operations is demonstrated in a generic 65 nm logic process. The proposed switch shows the robust operation for supply voltages ranging from VDD to $4{\times}VDD$. A cascaded voltage switch and a voltage doubler based charge pump generate the intermediate supply voltage levels required for the proposed high voltage switch. All the high voltage circuits developed in this work can be implemented using standard logic transistors without being subject to any voltage overstress.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.12
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• pp.1710-1715
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• 2014

In this paper, we propose a novel on-chip test logic for TSV fault detection in 3-dimensional integrated circuits. The proposed logic called OTT realizes the input signal delay-based TSV test method introduced earlier. OTT only includes one F/F, two MUXs, and some additional logic for signal delay. Thus, it requires small silicon area suitable for TSV testing. Both pre-bond and post-bond TSV tests are able to use OTT for short or open fault as well as small delay fault detection.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.191-194
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• 2000

A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.327-339
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• 1986

In this paper, a hardware compiler for symbolic description language(SDL) is proposed for logic design automation. Lexical analysis is performed for SDL which describes the behavioral characteristics of a digital system at the register transfer level by the proposed algorithm I. The algorithm I is proposed to get the expressions for the control unit and for the data transfer unit. In order to obtain the network description language(NDL) expressions equivalent to gate-level logic circuits, another algorithm, the the algorithm II, is proposed. Syntax analysis for the data formed by the algorithm I is also Performed using circuit elements such as D Flip-Flop, 2-input AND, OR, and NOT gates. This SDL hardware compiler is implemented in the programming language C(VAX-11/750(UNIX)), and its efficiency is shown by experiments with logic design examples.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.11
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• pp.94-104
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• 1995

In this paper, we present a new multi-level logic synthesis method for producing the multi-level circuits which can be easily tested by the pseudoexhaustive testing techniques. The method consists of four stages. In the first stage, it generates the minimum variable supports for each output of a multiple-output function. In the second stage, it removes the minimum variable supports which if used to implement the outputs, lead to inefficient pseudoexhaustive test. In the third stage, it determines the minimum variable support and logic (uncomplementary or complementary logic) for each output. In the fourth stage, it performs the multi-level logic synthesis so that each output. In the fourth stage, it performs the multi-level logic synthesis so that each output has the minimum variable support and logic determined in the third stage. To evaluate the performance and quality of the proposed method, we have experimented on the 56 benchmark examples. The results show that for 56 examples, our method obtains better results than MIS in terms of testability. Moreover, the method produces better results for 19 examples and the same results for 12 examples compared with MIS in terms of literal count although it has been developed to improve the testability.

• The Journal of Korean Association of Computer Education
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• v.10 no.6
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• pp.11-18
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• 2007

The proposed virtual laboratory system for digital logic circuits is composed of two main sessions, which are concept-learning session and virtual experiment session by virtual digital kit. During concept-learning session the learners can easily understand the important principles in the digital circuits to be performed. In addition, during virtual laboratory session the virtual experiments are performed by assembling and connecting the circuits on the virtual bread board, applying input voltages, making the output measurements, and comparing and transmitting the virtual experimental data. Every activity done during the virtual laboratory session is recorded on database and will be provided with the learners as a preliminary report form including personal information. Thus, the educators may check out the submitted preliminary report to estimate how well the learners understand the circuit operations. Finally, in order to show the validity of our virtual laboratory system we investigated and analysed the damage rate of real experimental equipment during class and assessed student performance on the five quizzes for one semester.