• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제3권1호
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• pp.44-51
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• 2003

Knowledge acquisition is a bottleneck in knowledge-based system implementation. Decision tree induction is a useful machine learning approach for extracting classification knowledge from a set of training examples. Many real-world data contain fuzziness due to observation error, uncertainty, subjective judgement, and so on. To cope with this problem of real-world data, there have been some works on fuzzy classification rule learning. This paper makes a survey for the kinds of fuzzy classification rules. In addition, it presents a fuzzy classification rule learning method based on decision tree induction, and shows some experiment results for the method.

• 한국정보통신학회논문지
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• 제11권3호
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• pp.491-499
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• 2007

본 논문에서는 Reed-Muller 전개식에 의한 3치 논리 회로를 설계하는 한 가지 방법을 제시하였다. 제시된 3치 논리 회로의 설계 방법은 Reed-Muller 전개식의 계수에 대하여 모든 변수의 차수를 검사하여 RME 모듈(Reed-Muller Expansions module)의 수를 최소화하는 최적의 제어 입력 변수의 순서를 결정한다. 최적의 제어 입력 변수의 순서는 회로 비용 행렬의 계산에 사용되며, 이 회로 비용 행렬의 계산 결과를 이용하여 Reed-Muller 전개식에 의한 RME 모듈의 나무 구조의 3치 논리 회로를 설계한다. 제시된 방법은 최적 제어 입력 변수를 찾는데 유일하게 단위시간 내에 수행되며, 컴퓨터 프로그램이 가능하고, 프로그래밍 수행 시간이 $3^n$이다.

• 한국정보통신학회논문지
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• 제23권6호
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• pp.711-718
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• 2019

이진결정도는 고장수목 해석에서 기존의 Boolean Logic 해석법의 잘 알려진 대체 방법이다. 고장수목의 규모가 커짐에 따라 계산에 필요한 컴퓨터 연산시간과 자원이 급격하게 증가한다. 이진결정도로부터 단절집합 및 최소단절 집합을 효과적으로 계산하기 위해 새로운 고장경로 탐색법과 고장경로 재구성 방법이 제안되었다. 고장경로 그룹화와 Bottom-Up 탐색법은 고장경로의 탐색에 효율적임을 증명하였고, 최소단절집합 계산을 위한 단절집합의 비교계산 횟수를 줄이기 위해 경로 재구성 방법을 사용할 수 있음을 증명하였다. 새로 제안된 방법을 적용하고, 기존의 근사확률 공식인 MCUB 확률공식과 동일한 새로운 ASDMP 확률공식을 사용하여 정상사상 확률을 계산 할 수 있다.

• 제어로봇시스템학회논문지
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• 제19권4호
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• pp.328-333
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• 2013

Since a slight malfunction of control systems in a nuclear power plant may cause huge catastrophes, such control systems usually have multiple redundancy and reliable features, and their reliability and availability should be analyzed and verified thoroughly. This paper performed the reliability analysis of the SPLC (Safety Programmable Logic Controller) that is under developed as the control systems for the next generation nuclear power plant. One of the key features of SPLC is that it has multiple redundancy modes as faults happen, which means the reliability analysis for one fixed redundant model is not enough to analyze the reliability of SPLC. With considering this reconfigurable concept, FTA (Fault Tree Analysis) was used to capture fault-relationship among sub-modules. The analysis results show that MTTF (Mean Time to Fault) of SPLC is 45,080 hours, which is a about 4.5 times longer than the regulation, 10,000 hours.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 추계학술대회 논문집
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• pp.1285-1293
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• 2008

Locking sheet is to display the contents of interlocking equipment for safe train drive in stations. It is being used as a basic information for interlocking equipment and for route control condition and the discussion for train operation between related parties. In spite of importance of this, there was no other way except depending on the work by hands from each stage(drawing, examination, discussion, approval) due to non-existing any tool. It is written it takes 30days from drawing to approval by procedures. However, it is required over the days in real time due to argument of each party. Furthermore on drawing of locking sheet, special conditions applied in accordance with situations of each station occasionally are different depending on the person in charge. Therefore, it is urgent to make up Logic Tree to accept special conditions of all stations. Automation Program for Drawing and Examination of Locking Sheet is to improve inefficient interlocking operation which was operated by hands in accordance with custom as automated system. The target of this program is to minimize the processing time and potential errors by personal work and set up standards for Logic Tree of special condition.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제7권8호
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• pp.2042-2060
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• 2013

In wireless sensor networks (WSNs), energy efficiency is one of the most essential design considerations, since sensor nodes are resource constrained. Group communication can reduce WSNs communication overhead by sending a message to multiple nodes in one packet. In this paper, in order to simultaneously resolve the transmission security and scalability in WSNs group communications, we propose a hierarchical cluster-based secure and scalable group key management scheme, called HRKT, based on logic key tree and route key tree structure. The HRKT scheme divides the group key into cluster head key and cluster key. The cluster head generates a route key tree according to the route topology of the cluster. This hierarchical key structure facilitates local secure communications taking advantage of the fact that the nodes at a contiguous place usually communicate with each other more frequently. In HRKT scheme, the key updates are confined in a cluster, so the cost of the key updates is reduced efficiently, especially in the case of massive membership changes. The security analysis shows that the HRKT scheme meets the requirements of group communication. In addition, performance simulation results also demonstrate its efficiency in terms of low storage and flexibility when membership changes massively.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제2권1호
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• pp.20-25
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• 2002

This paper presents a genetic programming based evolutionary strategy for on-line adaptive learnable evolvable hardware. Genetic programming can be useful control method for evolvable hardware for its unique tree structured chromosome. However it is difficult to represent tree structured chromosome on hardware, and it is difficult to use crossover operator on hardware. Therefore, genetic programming is not so popular as genetic algorithms in evolvable hardware community in spite of its possible strength. We propose a chromosome representation methods and a hardware implementation method that can be helpful to this situation. Our method uses context switchable identical block structure to implement genetic tree on evolvable hardware. We composed an evolutionary strategy for evolvable hardware by combining proposed method with other's striking research results. Proposed method is applied to the autonomous mobile robots cooperation problem to verify its usefulness.

• 전자공학회논문지B
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• 제32B권8호
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• pp.1057-1063
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• 1995

This paper describes an approach for constucting a Rectilinear Steiner Tree (RST) derivable from a Minimum Spanning Tree (MST), using Associative Processor (AP). We propose a fast parallel algorithm using AP's basic algorithms which can be realized by the processing capability of rudimentary logic and the selective matching capability of Content- Addressable Memory (CAM). The main idea behind the proposed algorithm is to maximize the overlaps between the consecutive edges in MST, thus minimizing the cost of a RST. An efficient parallel linear algorithm with O(n) complexity to construct a RST is proposed using an algorithm to find a MST, where n is the number of nodes. A node insertion method is introduced to allow the Z-type layout. The routing process which only depends on the neighbor edges and the no-rerouting strategy both help to speed up finding a RST.

• International Journal of Fuzzy Logic and Intelligent Systems
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• 제2권3호
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• pp.194-197
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• 2002

This paper considers the problem of routing connections in a optical multi tree networks using WDM (Wavelength Division Multiplexing), where each connection between a pair of nodes in the network is assigned a path through the network and a wavelength on that path, so that connections whose paths share a common link in the network are assigned different wavelengths. The problem of optimal coloring of the paths on the optical multi-networks is NP-hard[1], but if that is the coloring of all paths, then there exists efficient polynomial time algorithm. In this paper, using a "divide & conquer" method, we give efficient algorithm to assign wavelengths to all the paths of a tree network based on the theory of [7]. Here, our time complexity is 0(n4log n).