• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1554-1563
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• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.295-298
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• 2010

Linear Temporal Logic synthesis 는 LTL formula 로 표현된 요구 사항으로부터 그것을 만족하는 시스템을 만들어낸다. 이러한 synthesis 과정은 2EXPTIME-complete 이 요구 되지만 GR formula 라는 특수한 형태를 사용함으로써 복잡도를 Polynomial 시간으로 줄일 수 있다. LTL synthesis 는 작업 공간, 로봇이 취하는 센서 정보와 액션의 종류, 상위 수준의 작업 명세를 입력으로 받아 GR formula 형태로 변환하고, 기대되는 작업이 실현 가능하다면 그것을 성취할 수 있는 오토마타를 생성해낸다. Synthesis 알고리즘을 구현한 LTLMoP 라는 도구를 이용하여 LTL synthesis 과정을 보이고 화성 행궁의 미아 찾기 로봇 작업 계획을 구현한다. 마지막으로 시뮬레이션 과정을 통해 기대하는 작업을 성공적으로 성취할 수 있음을 보인다.

• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.777-786
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• 1995

This paper describes several algorithms for technology mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improve the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as node-pair decomposition, merging fanin, unified reduction and multiple output decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique［8］. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of the Korea Institute of Military Science and Technology
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• v.21 no.4
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• pp.437-446
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• 2018

This paper describes the real-time logic implementation of orthogonal matching pursuit(OMP) algorithm for compressive sensing digital receiver. OMP contains various complex-valued linear algebra operations, such as matrix multiplication and matrix inversion, in an iterative manner. Xilinx Vivado high-level synthesis(HLS) is introduced to design the digital logic more efficiently. The real-time signal processing is realized by applying dataflow architecture allowing functions and loops to execute concurrently. Compared with the prior works, the proposed design requires 2.5 times more DSP resources, but 10 times less signal reconstruction time of $1.024{\mu}s$ with a vector of length 48 with 2 non-zero elements.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.411-421
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• 1988

This paper offers a method to design CCD four-valued circuits using the tabular method. First, the four-valued logic function is decomposed by hand-calculation or computer program. Nest, the algorithm is derived form the tabular method based on the decomposition process to realize the DDC four-valued circuit. According to this algorithm, the two-variable four valued logic function is decomposed and realized by CCD network with four basic gates. The synthesis method in this paper proves that the number of devices and cost is considerably reduces as compared with the existing methods to realize the same logic functions.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3067-3069
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• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.4
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• pp.210-215
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• 2004

This paper proposes an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph, a Boolean function is derived, whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This function is then used to determine the minimum cost feedback vertex set. Even though computing the minimum cost satisfying assignment for a Boolean function remains an NP-hard problem, it is possible to exploit the advances made in the area of Boolean function representation in logic synthesis to tackle this problem efficiently in practice for even reasonably large sized graphs. The algorithm has obvious application in flip-flop selection for partial scan. The algorithm proposed in this paper is the first to obtain the MFVS solutions for many benchmark circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• Aerospace Engineering and Technology
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• v.12 no.2
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• pp.131-139
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• 2013

This paper describes the design and implementation of a small avionics unit based on soft CPU. A small avionics unit is developed with the soft CPU which can be wholly implemented in FPGA using logic synthesis. Design and integration of a modular architecture for versatile, reconfigurable and re-adaptable is presented with the Nios-II processor. To gain modular architecture, both at main board and sub-board level, attention has been paid to the selection of interfaces and an adequate data and power bus.