• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.504-511
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• 2003

The property of circuit symmetry has long been applied to the Problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power minimization, utilizing circuit symmetries. First, we analyze and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose effective transformation algorithms to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.131-137
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• 2000

In this paper, as a compatible software radio transmission system, Digital-Radio conversion system which can directly change the digital signal generated by the logic circuit into radio signal is proposed. By the vector synthesis method, the digital signals can change directly into radio signal. If such a circuit is realized, RF circuit and an antenna can be composed by the simple one device, and the radio is directly controlled and performed by the software processing which is the essence of software radio. This Digital-Radio conversion system of this paper give many number of communication channels being offered by PN code and offer a hardware design flexibility by digitization, therefore it decrease the percentage ratio of hardware of system and give a more flexible function of software basis. In this paper, the principle of digital to radio signal generation algorithm is explained and the performance characteristics of proposed algorithm is shown in time base by the computer simulation method.

• Journal of the Korean Chemical Society
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• v.56 no.2
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• pp.236-245
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• 2012

The main mycobacterial infection in human is tuberculosis caused by Mycobacterium tuberculosis. Tuberculosis is the leading infectious cause of death in the world. Therefore there is continuing and compelling need for new and improved treatment for tuberculosis. The entire logic towards design of new compounds containing 4-hydroxy-N'-(1,3-thiazoldin- 2-yldene)benzohydrazide moiety is basically for superior antimycobacterial activity. The recent advances in QSAR and computer science have provided a systematic approach to design a structure of any compound and further, the biological activity of the compound can be predicted before synthesis. The 3D-QSAR studies for the set of 4-hydroxy-N'-(1,3-thiazoldin- 2-yldene)benzohydrazide and their derivatives were carried out by using V-life MDS (3.50). The various statistical methods such as Multiple Linear Regression (MLR), Partial Least Square Regression (PLSR), Principle Component Regression(PCR) and K nearest neighbour (kNN) were used. The kNN showed good results having cross validated $r^2$ 0.9319, $r^2$ for external test set 0.8561 and standard error of estimate 0.2195. The docking studies were carried out by using Schrodinger GLIDE module which resulted in good docking score in comparison with the standard isoniazid. The designed compounds were further subjected for synthesis and biological evaluation. Antitubercular evaluation of these compounds showed that (4.a), (4.d) and (4.g) found as potent inhibitor of H37RV.

• Journal of KIISE:Software and Applications
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• v.32 no.12
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• pp.1178-1191
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• 2005

In this paper, we propose a synthesis method of software fault tree from software requirements specification written in NuSCR formal specification language. The software fault tree, proposed in this paper, reflects requirements on both structure and behavior and it is an integrated form. The software fault tree can be used for analyzing safety in the view of structure and behavior. We propose templates for each components in NuSCR specification language and a synthesis method of software fault tree using the templates. The research was applied into the main trip logic of the reactor protection system of ARP1400, the Korean next generation nuclear reactor system, developed by KNICS. And we evaluate feasibility of our approach through this case study.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.120-120
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• 2011

Graphene is a carbon based material and it has great potential of being utilized in various fields such as electronics, optics, and mechanics. In order to develop graphene-based logic systems, graphene field-effect transistor (GFET) has been extensively explored. GFET requires supporting devices, such as volatile memory, to function in an embedded logic system. As far as we understand, graphene has not been studied for volatile memory application, although several graphene non-volatile memories (GNVMs) have been reported. However, we think that these GNVM are unable to serve the logic system properly due to the very slow program/read speed. In this study, a GVM based on the GFET structure and using an engineered graphene channel is proposed. By manipulating the deposition condition, charge traps are introduced to graphene channel, which store charges temporarily, so as to enable volatile data storage for GFET. The proposed GVM shows satisfying performance in fast program/erase (P/E) and read speed. Moreover, this GVM has good compatibility with GFET in device fabrication process. This GVM can be designed to be dynamic random access memory (DRAM) in serving the logic systems application. We demonstrated GVM with the structure of FET. By manipulating the graphene synthesis process, we could engineer the charge trap density of graphene layer. In the range that our measurement system can support, we achieved a high performance of GVM in refresh (>10 ${\mu}s$) and retention time (~100 s). Because of high speed, when compared with other graphene based memory devices, GVM proposed in this study can be a strong contender for future electrical system applications.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.238-241
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• 2000

This paper describes an equalizer using the DFE (Decision Feedback Equalizer) structure, CMA. (Constant Modulus Algorithm) and LMS (Least Mean Square) algorithms. We employ high speed multipliers, square logics and many CSAs (Carry Save Adder) for high speed operations. We have developed floating-point models and fixed-point models using the COSSAP$\^$TM/ CAD tool and developed VHDL models. We have peformed logic synthesis using the SYNOPSYS$\^$TM/ CAD tool and the SAMSUNG 0.5 $\mu\textrm{m}$ standard cell library (STD80). The total number of gates is about 130,000.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.585-588
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• 2004

This paper describes design and verification of the motion estimation and compensation unit using full search algorithm. Video processor is the key device of video communication systems. Motion estimation is the key module of video processor. The technologies of motion estimation and compensation unit are the core technologies for wireless video telecommunications system, portable multimedia systems. In this design, Verilog simulator and logic synthesis tools are used for hardware design and verification. In this paper, motion estimation and compensation unit are designed using FPGA, coded in Verilog HDL, and simulated and verified using Xilinx FPGA.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.651-654
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• 2005

In this paper, we designed ECC(Elliptic Curve Cryptographic) Processor with Bus-splitting mothod for embedded SoC. ECC SIP is designed by VHDL RTL modeling, and implemented reusably through the procedure of logic synthesis, simulation and FPGA verification. To communicate with ARM9 core and SIP, we designed SIP bus functional model according to AMBA AHB specification. The design of ECC Processor for platform-based SoC is implemented using the design kit which is composed of many devices such as ARM9 RISC core, memory, UART, interrupt controller, FPGA and so on. We performed software design on the ARM9 core for SIP and peripherals control, memory address mapping and so on.

• Journal of Urban Science
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• v.6 no.2
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• pp.11-16
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• 2017

Giuseppe Terragni was one of the founding member and a leading Italian Rationalist pursued a new and more rational synthesis between the nationalistic values of Italian Classicism and structural logic of the machine age. Casa Giuliani Frigerio, a four-story apartment housing in Como, is one of his last major work and is worth to investigate the composition of facades in terms of ambiguity. Unlike the Casa del Fascio, it is never possible to read an priori whole and to allow static and unified readings in a traditional alignment. Due to its misalignments found within the facades of Casa Giuliani Frigerio, it is evident to present unstable and disjunctive readings. These distinctive facades are read as layers applied onto some equally unstable underlying layer and form an ensemble of unexpected unity.