• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.75-82
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• 2015

This paper presents a new technique for enhancing power quality by reducing harmonics in the neutral conductor. Three-Phase Four-Wire (3P4W) system is commonly used where single and three phase loads are connected to Point of Common Coupling (PCC). Due to unbalance loads, the 3P4W distribution system becomes unbalance and current flows in the neutral conductor. If loads are non-linear, then the harmonic content of current will flow in neutral conductor. The neutral current that may flow towards transformer neutral point is compensated by using a series active filter. In order to reduce the harmonic content, the series active filter is connected in series with the neutral conductor by which neutral and phase current harmonics are reduced significantly. In this paper, solar PV based inverter circuit is proposed for compensating neutral current harmonics. The simulation is carried out in MATLAB/SIMULINK and also an experimental setup is developed to verify the effectiveness of the proposed method.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.9
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• pp.1-7
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• 2014

Brushless Direct Current(BLDC) Motor is essential to measure a rotor position because of that this motor type needs to synchronize the rotor's position and changeover phase current instead of a brush and commutator used on the existing dc motor. Recently, many researches have studied on sensorless control drive for BLDC motor. The conventional control methods are a compensation value dq, Kalman filter, Fuzzy logic, Neurons neural network, and the like. These methods has difficulties of detecting BEMF accurately at low speed because of low BEMF voltage and switching noise. And also, the operation is long and complex. So, it is required a high-performance microprocessor. Therefore, it is not suitable for a small BLDC motor sensorless drive. This paper presents control methods suitable for economic small BLDC motor sensorless drive which are an improved design of the BEMF detection circuit, simplifying a complex algorithm and computation time reduction. The improved motor sensorless drive is verified stability and validity through being designed, manufactured and analyzed.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• Journal of Electrical Engineering and Technology
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• v.1 no.1
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• pp.63-72
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• 2006

The purpose of this raper is to address the negative impedance instability in DC/DC converters. We present the negative impedance instability of PWM DC/DC converters loaded by constant power loads (CPLs). An approach to design digital controllers for DC/DC converters Is presented. The proposed method, called Power Alignment control technique, is applied to DC/DC step-down choppers operating in continuous conduction or discontinuous conduction modes with CPLs. This approach uses two predefined state variables instead of conventional pulse width modulation (PWM) to regulate the output voltage. A comparator compares actual output voltage with the reference and then switches between the appropriate states. It needs few logic gates and comparators to be implemented thus, making it extremely simple and easy to develop using a low-cost application specific integrated circuit (ASIC) for converters with CPLs. Furthermore, stability of the proposed controllers using the small signal analysis as well as the second theorem of Lyapunov is verified. Finally, simulation and analytical results are presented to describe and verify the proposed technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.89-96
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• 2002

In this paper, the ADI(Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and the architecture designed through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using $0.6{\mu}m$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• The Journal of the Acoustical Society of Korea
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• v.19 no.3
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• pp.11-19
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• 2000

This research deals with the implementation procedures of a chorus processing DSP for karaoke system. It is necessary to compress the chorus data to store as many choruses as we can. We apply MPEG-1 audio algorithm to compress the chorus data. And the chorus system must be accompanied with the karaoke that can change the key and the tempo. So the chorus DSP must be able to change the key and tempo of the chorus data. We apply SOLA (Synchronized Overlap and Add) to do it. We designed the chorus DSP that can compress the chorus, change the key and tempo. And we verified the chorus DSP logic using FPGA. The used FPGA are two FLEX10K100s made by ALTERA. Finally we make the ASIC chip of chorus DSP and verify its operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.817-820
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• 2008

Development of computer and internet has permitted cyber education transcending time and space, which escapes traditional classroom. As a result, the study of learner's own leading in Web-based instruction environment can be possible. In order to perform it effectively, suitable helps and advices, called scaffolding, must be offered. In this pater, we select a principle of computer in information technology basic subject of technical high school, and design and implement the web contents that provide the proper scaffolding for learners.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1575-1582
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• 1998

Reed-Solomon(RS) code which is especially effective against burst error is studied as a forward error correction technique in this ppaer. The circuits of RS encoder and decoder for ASIC implementation are designed and presented employing modified Euclid's algorithm. The functionalities of the designed circuits are verified though C programs which simulates the circuits over the various errors and erasures. The pipelined circuits using systolic arrays are designed for ASIC realization in VHDL, and verified through the logic simulations. Finally the circuit synthesis of RS encoder and decoder can be achieved.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.11
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• pp.650-656
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• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.6
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• pp.251-255
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• 2015

In this paper, we propose a fuse controller which is used for storing the optimal value or the correction value for the surrounding product of the IoT applications and it is implemented serial communication circuit using a single pin. Because of the proposed single pin protocol is simpler in the hardware than the conventional $I^2C$ and SPI using two or more pins, it is suitable for the area of small amount of data transmission. The function of the one pin protocol is verified by logic simulation and the FPGA test board and it is fabricated using CMOS 0.35um technology. It is expected to use the IoT product that require the low power consumption and simple hardware.