• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.509-521
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• 1988

In the designs of integrated circuits, the buffer circuits used for driving a large capacitive load from minimum-structured logic circuit outputs have important effects upon system throughputs. Therefore it is important to optimize the buffer circuits. In this paper, the principle of designing CMOS buffer circuits which have the minimum delay and drive the given capacitive load is discussed. That is, the effects of load capacitance upon rise time, fall time, and delay of the CMOS inverter and the effects of parasitic capacitances are finely analysed to calculate the requested minimum-delay CMOS buffer condition. This is different from the method by C.A. Mead et. al.[2.3.4.]which deals with passive-load-nMOS buffers. Large channel width MOS transistor stages are necessary to drive a large capacitive load. The effects of polysilicon gate resistances of such large stages upon delay are also analysed.And, the area of buffer circuits designed by the proposed method is smaller than that of buffer circuits designed by C.A. Mead's method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.7
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• pp.1259-1265
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• 2006

In this paper, we propose a combined synthetic algorithm of the logic level for high speed FPGA design. The algorithm divides critical path to reduce delay time and generates a circuit which the divided circuits execute simultaneously. This kernel selection algorithm is made by C-langage of SUN UNIX. We compare this with the existing FlowMap algorithm. This proposed algorithm shows result on 33.3% reduction of delay time by comparison with the existing algorithm.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.139-142
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• 2000

In this paper, the ADI (Adaptive De-interlacing) algorithm is proposed, which improves visually and subjectively horizontal and vertical edges of the image processed by the ELA(Edge Line-based Average) method. This paper also proposes a VLSI architecture for the proposed algorithm and designed the architecture through the full custom CMOS layout process. The proposed algorithm is verified using C and Matlab and implemented using 0.6$\mu\textrm{m}$ 2-poly 3-metal CMOS standard libraries. For the circuit and logic simulation, Cadence tool is used.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.865-868
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• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.161-165
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• 2004

In this paper, an 8bit wave pipelined adder using the static CMOS plus Edge-Sensing Completion Detection Logic is presented. The clockless wave-pipelining algorithm was implemented in the circuit design. The Edge-Sensing Completion Detection (ESCD) in the algorithm is consisted of edge-sensing circuits and latches. Using the algorithm, skewed data at the output of 8bit adder could be aligned. Simulation results show that the adder operates at 1GHz in $0.35{\mu}m$ CMOS technology with 3.3V supply voltage.

• Journal of the Korea Convergence Society
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• v.4 no.2
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• pp.43-50
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• 2013

Sliding mode control(SMC) are carried out in this literature. And to make the controllers perform better, fuzzy logic was chosen,it makes PID controller auto-tuning parameters and reduced the chattering problem of sliding mode control. Since SMC take error and derivative of error as inputs, after comparison some results are obtained.PID controller response faster yet sliding mode control is much steadier. However certain problems cannot be ignored that the chattering phenomenal cannot be reduced entirely and this motion may hurt the machine; this project only considered a simple system, there is no guarantee PID can work as well as in this case for a much more complex system. MATLAB simulink was the main approach to obtain the performance of the two controllers: to observe the control output of the two controllers, electric circuit and special controllers are designed and tested in MATLAB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1056-1063
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• 1994

In this paper a content addressable memory (CAM) is designed by adopting best-match method. It has a single processing element(PE) architecture with high computational efficiency and throughput. It is composed of three main functional blocks(input MUX, best-match CAM, control part). It support fully parallel processing. Logic simulation is completed by using QUICKSIM, Circuit simulation is performanced by using HSPICE. Its layout is based on the ETRI 3 m n-well process design rules. Its maximum operating frequency is 20 MHz.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1221-1229
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• 1996

This paper proposes a heuristic algorithm for low power implementation of combinational circuits. Selecting an input variable for a given function, the proposed algorithm performs Shannon exansion with respect to the variable to reduce the number of gates in the subcircuit realizing the coffactor function, reducting the power dissipation of the implemented circuit. experimental results for the MCNC benchmarks show that the proposed algorithm is effective by generating the circuits consuming the power 48.9% less on the average, when compared to the previous algorithm based on precomputation logic.