• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.10
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• pp.89-96
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• 2003

In this paper, a CCSDS(Consultative Committee for Space Data Systems) telecommand(TC) decryptor for the security of geostationary communications satellite was implemented. For the confidentiality of CCSDS TC datalink security, Option-A which implements the security services below the transfer sublayer was selected. Also CFB(Cipher Feedback) operation mode of DES(Data Encryption Standard) was used for the encryption of 56-bit data bits in 64-bit codeblock. To verify Decryptor function, the DES CFB logic implemented on A54SX32 FPGA(Field Programmable Gate Array) was integrated with interface and control logics in a PCB(Printed Circuit Board). Using a function test PC, the encrypted codeblocks were generated, transferred into the decryptor, decrypted, and the decrypted codeblocks were transmitted to the function test PC, and then compared with the source codeblocks. Through LED(Light Emitting Diode) ON operation by driving the relay related to Op-code decoded and the comparison between the codeblock output waveforms measured and those simulated, the telecommand decryptor function was verified.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.480-480
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• 2000

In this paper, we proposed a fuzzy-neuro controller to control the speed of wound rotor induction motor with slip energy recovery. The speed is limited at some range of sub-synchronous speed of the rotating magnetic field. Control speed by adjusting resistance value in the rotor circuit that occurs the efficiency of power are reduced, because of the slip energy is lost when it passes through the rotor resistance. The control system is designed to maintain efficiency of motor. Recently, the emergence of artificial neural networks has made it conductive to integrate fuzzy controllers and neural models for the development of fuzzy control systems, Fuzzy-neuro controller has been designed by integrating two neural network models with a basic fuzzy logic controller. Using the back propagation algorithm, the first neural network is trained as a plant emulator and the second neural network is used as a compensator for the basic fuzzy controller to improve its performance on-line. The function of the neural network plant emulator is to provide the correct error signal at the output of the neural fuzzy compensator without the need for any mathematical modeling of the plant. The difficulty of fine-tuning the scale factors and formulating the correct control rules in a basic fuzzy controller may be reduced using the proposed scheme. The scheme is applied to the control speed of a wound rotor induction motor process. The control system is designed to maintain efficiency of motor and compensate power factor of system. That is: the proposed controller gives the controlled system by keeping the speed constant and the good transient response without overshoot can be obtained.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.1
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• pp.70-75
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• 2014

This paper presents a IR-UWB(Impulse Radio Ultra-Wide Band) transceiver circuit for data communication and real time location system. The UWB receiver is designed to OOK(On-Off Keying) modulation for energy detection. The UWB pulse generator is designed by digital logic. And the Gaussian filter is adopted to reject side lobe in transmitter. The measured sensitivity of the receiver is -65 dBm at 4 GHz with 1 Mbps PRF(Pulse Repetition Frequency). And the measured energy efficiency per pulse is 20.6 pJ/bit. The current consumption of the receiver and transmitter including DA is 27.5 mA and 25.5 mA, respectively, at 1.8 V supply.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.14 no.4
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• pp.268-275
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• 2014

In future, hospitals are expected to automatically issue remote transcriptions. Many general hospitals are planning to encrypt their medical database to secure personal information as mandated by law. The electronic medical record system, picture archiving communication system, and the clinical data warehouse, amongst others, are the preferred targets for which stronger security is planned. In the near future, medical systems can be assumed to be automated and connected to remote locations, such as rural areas, and islands. Connecting patients who are in remote locations to medical complexes that are usually based in larger cities requires not only automatic processing, but also a certain amount of security in terms of medical data that is of a sensitive and critical nature. Unauthorized access to patients' transcription data could result in the data being modified, with possible lethal results. Hence, personal and sensitive data on telemedicine and medical information systems should be encrypted to protect patients from these risks. Login passwords, personal identification information, and biological information should similarly be protected in a systematic way. This paper proposes the use of electronic acupuncture with a built-in multi-pad, which has the advantage of being able to establish a patient's physical condition, while simultaneously treating the patient with acupuncture. This system implements a sensing pad, amplifier, a small signal drive circuit, and a digital signal processing system, while the use of a built-in fuzzy technique and a control algorithm have been proposed for performing analyses.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.1-10
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• 1998

This paper is to propose an algorithm named as DYSAC to find the critical path(the longest sensitizable path) in a large digital circuit, whose purpose is to reduce the time to find critical path and to find critical paths of the circuits for which the previous methods could not find one. Also a set of path sensitization criteria named as DYPSEC is proposed, which is used to select a path from input to the output inside the DYSAC. The DYSAC consists of two sub-algorithms; the level assignment algorithm to assign a level to each node and the critical path selection algorithm to select the sensitizable path. The proposed algorithm was implemented with C-language on SUN Sparc and applied to the ISCAS'85 benchmark circuits to make sure if it works correctly and finds the correct critical path. Also, the results from the experiments were compared to the results from the previous works. The comparison items were the ability to find the critical path and the speed, in both of which the proposed algorithm in this paper shows better results than others.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.6
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• pp.70-76
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• 2015

This paper introduces an FPGA self-test architecture reusing FPGA boundary scan chain as self-test circuits. An FPGA boundary scan cell is two or three times bigger than a normal boundary scan cell because it is used for configuring the function of input/output pins functions as well as testing and debugging. Accordingly, we analyze the architecture of an FPGA boundary scan cell in detail and design a set of built-in self-test (BIST) circuits in which FPGA boundary scan chain and a small amount of FPGA logic elements. By reusing FPGA boundary scan chain for self-test, we can reduce area overhead and perform a processor based on-board FPGA testing/monitoring. Experimental results show the area overhead comparison and simulation results.

• The Transactions of the Korea Information Processing Society
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• v.4 no.2
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• pp.628-638
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• 1997

This paper describes an implementation of fault simulator that can switch level fault models such as transistor stuck-open and stuck-closed faults as well as stuck-at faults. It overcomes the limitation when only stuck-at faults are used in VLSI circuits. Signal flow of a transistor switch is bidirectional in its nature, but most of signal flows in a switch level circuits, about 95%, are in one direction. This fault simulator focuses on the way which changes a switch level circuit into a graph model with two directed edges. Two paths from Vdd to ground and from ground to directions. Logic simulation is performed along dominant signal flows. The switch level fault simulation estimates the dominant path by injecting switch-level fualts, and pattern vectors are used for faults simulation. Experimental results are shown to demonstrate correctness of the fault simulator.

• Journal of IKEEE
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• v.20 no.3
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• pp.260-264
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• 2016

The MAX77846, which is compatible with MAX77826, is a sub-power management IC (PMIC) for the latest Wearable Watch and 3G/4G smart phones. The MAX77846 contains N-MOSFET (N channel Metal-Oxide Semiconductor Field-Effect Transistor), a high-efficiency regulator, and comparator, etc to power up peripherals. The MAX77846 also provides power on/off control logic for complete flexibility and an $I^2C$ (Inter Integrated Circuit) serial interface to program individual regulator output voltages. In this paper, the simplified power macro-model based on MAX77846 is designed to verify the performance of the battery voltage in terms of current and time, and simulated by using of the LTspice. In addition, it is verified how much time can the charged battery capacity for Samsung Galaxy Gear 2 be used to operate a specified function after measuring the currents flowing to carry out the main functions in real time, which will be applicable to design parameters for the advanced power module