• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권9호
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• pp.545-551
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• 2004

CBTC(Communication Based Train Control) System can improve train operation efficiency by realizing moving block system which makes a continuous train interval control in accordance with the position and speed of train. Adopting radio transmission to make a continuous detection of train position and transmit the control data from the ground to a train, CBTC needs dedicated train operation and control algorithm which should be quite different from the conventional track-circuit-based train control system. This paper provides a train operation display and control algorithm for CBTC system in making train interval control, train route control and train supervision. Signalling pattern diagram is devised to analyze the train interval control mechanism of moving block system, and interlocking logic is devised to represent the train route control mechanism of moving block system. For train supervision, train occupation status on railway are displayed by using the segment which virtually divide the whole railway. The proposed method has been successfully applied to the development of CBTC system for the standardized AGT(automatic guided transit) which is under construction now in Korea, and also can be applied to any other CBTC system.

• 전자공학회논문지A
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• 제33A권10호
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of Electrical Engineering and Technology
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• 제1권1호
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• pp.63-72
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• 2006

The purpose of this raper is to address the negative impedance instability in DC/DC converters. We present the negative impedance instability of PWM DC/DC converters loaded by constant power loads (CPLs). An approach to design digital controllers for DC/DC converters Is presented. The proposed method, called Power Alignment control technique, is applied to DC/DC step-down choppers operating in continuous conduction or discontinuous conduction modes with CPLs. This approach uses two predefined state variables instead of conventional pulse width modulation (PWM) to regulate the output voltage. A comparator compares actual output voltage with the reference and then switches between the appropriate states. It needs few logic gates and comparators to be implemented thus, making it extremely simple and easy to develop using a low-cost application specific integrated circuit (ASIC) for converters with CPLs. Furthermore, stability of the proposed controllers using the small signal analysis as well as the second theorem of Lyapunov is verified. Finally, simulation and analytical results are presented to describe and verify the proposed technique.

• 대한전자공학회논문지SD
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• 제47권5호
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• pp.48-55
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• 2010

반도체 설계기술의 발달로 구현 회로가 복잡해지고, 동작속도가 크게 증가함에 따라, 반도체 이후 (post-silicon) 설계 단계에서 repair를 위한 기간 및 비용이 크게 증가하고 있다. 본 논문에서는 예비 셀을 이용한 repair 방법을 통해 설계 오류로 인한 repair시 혹은 설계 변경 시에 전체 재설계를 최소화하는 방법을 제안하였다. 또한 예비 셀을 이용한 설계 변경 과정에서 repair layer에 설계 변경을 국한하여 mask 비용과 time-to-market을 줄이는 방법을 개발하였다. 또한 회로 분할을 통해 repair 과정에서 사용하는 예비회로의 비용을 줄일 수 있도록 한다.

• 전기전자학회논문지
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• 제2권2호
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• pp.166-172
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• 1998

스위치드 리럭턴스 전동기는 구조가 간단하고 회전자관성이 작으며 고효율을 가지는 전동기이다. 그러나 회전자 위치각에 적절한 상여자 신호를 동기화하기 위해서는 위치센서가 필수적이다. 이 위치센서로 인하여 구동시스템의 가격상승과 열악한 환경에서 시스템의 신뢰성이 저하되는 문제점을 가지게 된다. 본 논문에서는 위치 및 속도센서가 없는 스위치드 리럭턴스 전동기의 속도제어 시스템을 연구하였다. 센서리스 SRM의 안정된 속도제어를 위하여 회전자 위치검출을 상전류 및 변화율 검출로부터 구하였으며 속도오차에 대하여 도통각 주기폭을 변동하는 속도제어 시스템을 제안하였다. 이 구동시스템은 위치결정회로 속도제어기, 디지탈논리 정류자, 스위칭각 제어기와 인버터로 구성된다. 제안된 시스템은 실험을 통하여 성능을 검증하였다.

• 대한전자공학회논문지SD
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• 제39권7호
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• pp.89-96
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• 2002

본 논문은 ELA알고리듬의 수평방향 및 수직방향과 대각선 방향을 판단하여 수평 윤곽선 및 수직 윤곽선 특성을 시각적인 면과 객관적인 면에서 개선한 ADI(adaptive de-interlacing)알고리듬을 제안하고, 제안한 알고리듬에 대한 수직을 전개, 이를 C, Matlab을 이용하여 검증하였다. 제안한 알고리듬의 구조를 $0.6{\mu}m$ 2-poly 3-metal CMOS 표준 라이브러리를 적용하고 Cadence툴을 이용하여 회로 및 논리 시뮬레이션을 수행하고 레이아웃을 작성하였다.

• ETRI Journal
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• 제42권3호
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• pp.376-387
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• 2020

Massive computation of the reconstruction algorithm for compressive sensing (CS) has been a major concern for its real-time application. In this paper, we propose a novel high-speed architecture for the orthogonal matching pursuit (OMP) algorithm, which is the most frequently used to reconstruct compressively sensed signals. The proposed design offers a very high throughput and includes an innovative pipeline architecture and scheduling algorithm. Least-squares problem solving, which requires a huge amount of computations in the OMP, is implemented by using systolic arrays with four new processing elements. In addition, a distributed-arithmetic-based circuit for matrix multiplication is proposed to counterbalance the area overhead caused by the multi-stage pipelining. The results of logic synthesis show that the proposed design reconstructs signals nearly 19 times faster while occupying an only 1.06 times larger area than the existing designs for N = 256, M = 64, and m = 16, where N is the number of the original samples, M is the length of the measurement vector, and m is the sparsity level of the signal.

• Bulletin of the Korean Chemical Society
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• 제35권12호
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• pp.3437-3442
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• 2014

A well-known carbazole-based precursor (probe 1) was used for the detection of cysteine/homocysteine and fluoride. Probe 1 shows a "turn-on" response to cysteine/homocysteine and fluoride via enhancement in emission intensity at 442 nm and 462 nm respectively, in solutions and living cells. Furthermore, probe 1 behaves as a fluorescent molecular switch between cysteine/homocysteine and fluoride as the chemical inputs, which have been used for the development of a combinatorial logic circuit and a molecular keypad lock.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 춘계학술발표회논문집(2)
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• pp.637-642
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• 1996

This paper presents the analysis results for the core degradation processes and the fission product release of the PHEBUS FPT0 experiment using MELCOR1.8.3. The objective of this study is to assess models associated with the core damage and fission product behavior in MELCOR. The calculation results were much improved through sensitivity studies. Thermal/hydraulic behavior in the core and the circuit was well predicted under the intact core geometry. In non-eutectic model case. the UO$_2$ dissolution model in the MELCOR always showed such a tendency that the resulting dissolved UO$_2$ mass was small at the highly oxidized condition due to the model logic. Total H$_2$ generation mass was underpredicted because the stiffner was not modeled and the liner in the shroud was not allowed to be oxidized in MELCOR. Some difficulties were found in modeling the activation product were solved by manipulating the RN input associated with the initial fission product inventory. These problem were occurred because there are no control rod model in MELCOR. Generally the fission product release ratio showed a similar trend compared with the measured data except the activation product. which have no model to simulate in MELCOR.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.