• ETRI Journal
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• 제36권1호
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• pp.89-98
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• 2014

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field-effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design.

• 조명전기설비학회논문지
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• 제28권9호
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• pp.1-7
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• 2014

Brushless Direct Current(BLDC) Motor is essential to measure a rotor position because of that this motor type needs to synchronize the rotor's position and changeover phase current instead of a brush and commutator used on the existing dc motor. Recently, many researches have studied on sensorless control drive for BLDC motor. The conventional control methods are a compensation value dq, Kalman filter, Fuzzy logic, Neurons neural network, and the like. These methods has difficulties of detecting BEMF accurately at low speed because of low BEMF voltage and switching noise. And also, the operation is long and complex. So, it is required a high-performance microprocessor. Therefore, it is not suitable for a small BLDC motor sensorless drive. This paper presents control methods suitable for economic small BLDC motor sensorless drive which are an improved design of the BEMF detection circuit, simplifying a complex algorithm and computation time reduction. The improved motor sensorless drive is verified stability and validity through being designed, manufactured and analyzed.

• 한국정보통신학회논문지
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• 제10권10호
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• pp.1804-1809
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• 2006

본 고에서는 디지털 회로의 저 전력소모의 설계와 구현에 관련된 디지털 전대역 회로 설계를 통해서 전반적인 전력 소모의 방법론과 이의 특성을 고찰하고자 한다. 디지털 집적회로의 설계는 광대하고 복잡한 영역이기에 우리는 이를 저전력 소모의 전반적인 회로 설계에 한정할 필요가 있다. 여기에는 로직회로의 합성과, 디지털 전대역 회로설계에 포함되어 있는 입력 clock 버퍼, 레치, 전압 Regulator, 그리고 케페시턴스와 전압기가 0.12 마이크론의 기술로 0.9V의 전압과 함께 쓰여져서 동적 그리고 정적 에너지 소모와 압력, 가속, Junction temperature 등을 모니터 할 수 있게 되어 있다.

• International Journal of Precision Engineering and Manufacturing
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• 제2권1호
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• pp.33-42
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• 2001

In switched reluctance motor(SRM) deives, the turn-on and turn-off angles of each phase switch should be accurately controlled for accuracy and efficiency. The accuracy of the switching angles is mainly dependent upon the resolution of the encoder and the sampling period of the microprocessor, that are used to provide the information of the rotor position and to implement a control algorithm of the SRM, respectively. Thus, the higher the speed of the SRM is increased, the larger the amount of the switching angle deviations are from preset turn-on and turn-off angles. Consequently, the motor can not be driven stably high speed region. There fore, a simples and low cost encoder suitable for the practical and stable SRM drive is proposed and the control algorithm to provide the switching signals using a simple digital logic circuit is also presented for a wide speed range operation.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2001년도 춘계학술대회 논문집
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• pp.102-105
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• 2001

The bending process for the curved tube can be developed by the hot metal extrusion machine with the multiple punches moving in the different velocity. The bending phenomenon has been studied to be occurred by the different of velocity at the die extrusion. The difference of velocity at the die exit section can be obtained by the different velocity of billets through the multi-hole container and by the welding of billets inside the porthole die chamber. The multiple billets are moving differently by the multiple extrusion punches controlled by PLC with the servo mechanism units. The results of the experiments show that the curved tube can be bended by the extrusion process and that the defects such as the distortion of section and the thickness change of thick tube, tile folding and wrinkling of thin tube can not be shown after the bending processing by the extrusion bending machine.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• 한국산학기술학회논문지
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• 제15권6호
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• pp.3821-3826
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• 2014

본 논문에서는 자동차용 솔레노이드 밸브의 전자장 해석 기반의 동특성 해석 모델을 통하여 성능을 향상시키는 방법을 제안한다. 종래의 솔레노이드 밸브의 요크와 플런저의 형상 최적설계를 통하여 저전류 고추력의 고성능 솔레노이드 모델을 도출하였다. 동특성 해석을 수행하기 위해 솔레노이드 밸브의 입력 전류 패턴을 분석하고, 이를 통해 밸브의 개폐시 속도, 추력 정보를 해석하였다. 입력 전류 패턴을 출력하는 제어로직의 회로모델과 스프링 및 댐핑 등을 고려할 수 있는 솔레노이드 밸브의 전자장 해석모델의 연동해석기반을 제안하여 입력전류 패턴의 변화가 밸브 동특성에 주는 영향을 분석할 수 있었다. 마지막으로 종래모델과 최적모델의 동특성 해석을 통하여 최적설계 모델의 성능이 개선됨을 확인하였다.

• Journal of Power Electronics
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• 제9권3호
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• pp.507-515
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• 2009

This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권9호
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• pp.545-551
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• 2004

CBTC(Communication Based Train Control) System can improve train operation efficiency by realizing moving block system which makes a continuous train interval control in accordance with the position and speed of train. Adopting radio transmission to make a continuous detection of train position and transmit the control data from the ground to a train, CBTC needs dedicated train operation and control algorithm which should be quite different from the conventional track-circuit-based train control system. This paper provides a train operation display and control algorithm for CBTC system in making train interval control, train route control and train supervision. Signalling pattern diagram is devised to analyze the train interval control mechanism of moving block system, and interlocking logic is devised to represent the train route control mechanism of moving block system. For train supervision, train occupation status on railway are displayed by using the segment which virtually divide the whole railway. The proposed method has been successfully applied to the development of CBTC system for the standardized AGT(automatic guided transit) which is under construction now in Korea, and also can be applied to any other CBTC system.

• 전자공학회논문지A
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• 제33A권10호
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.