• Title/Summary/Keyword: Locking Process

Search Result 126, Processing Time 0.15 seconds

Burst-mode Clock and Data Recovery Circuit in Passive Optical Network Implemented with a Phase-locked Loop (수동 광 가입자망에서의 위상고정루프를 이용한 버스트모드 클럭/데이터 복원회로)

  • Lee, Sung-Chul;Moon, Sung-Young;Moon, Gyu
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.45 no.4
    • /
    • pp.21-26
    • /
    • 2008
  • In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuits are implemented with 0.35um CMOS process technology. Locking dynamics is accomplished with instantaneous feature and data are sampled at an optimal timing. This is realized by seven different delay configurations, which are generated from precisely-controlled delay buffers. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

A DLL-Based Frequency Synthesizer for Generation of Various Clocks (가변 클록 발생을 위한 DLL 주파수 합성기)

  • 이지현;송윤귀;최영식;최혁환;류지구
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.8 no.6
    • /
    • pp.1153-1157
    • /
    • 2004
  • This paper describes a new programmable DLL_based frequency synthesizer. Generally, PLLs have been used for frequency synthesis. Inherent fast locking DLLs are also used for frequency synthesis. However, DLL needs a frequency multiplier for various frequencies. A conventional frequency multiplier used in DLL has a restriction in which a multiple is fixed. However, the proposed DLL can generate clocks which are from 6 times to 10 times of the reference clock. Frequency range of the proposed DLL is from 600MHz to 1GHz. The idea has been confirmed by HSPICE simulations in a $0.35-\mu\textrm{m}$ CMOS process.

A Fast-Locking All-Digital Frequency Multiplier (고속-락킹 디지털 주파수 증배기)

  • Lee, Chang-Jun;Kim, Jong-Sun
    • Journal of IKEEE
    • /
    • v.22 no.4
    • /
    • pp.1158-1162
    • /
    • 2018
  • A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

Properties of Inter-Locking Block with the Contents of the Fine Particles (미립분의 혼입율 변화에 따른 인터로킹 블록의 특성)

  • 이상태;김기철;신병철;이동남;한천구
    • Proceedings of the Korea Concrete Institute Conference
    • /
    • 1999.10a
    • /
    • pp.171-174
    • /
    • 1999
  • The objective of this study is to investigate the properties of fine particles in the process of producing crushed fine aggregates under various fine particle contents. According to the test results, when fine particles are added as substitution of aggregates by about 10%, it shows that the qualities of interlocking block such as compressive strength, flexural strength and absorption ratio are improved. The application of fine particles provide various advantages in the sides of recycling of materials

  • PDF

Lock-Acquisition Scheme for Arbitrary Replica Delay in High-Speed DLLs (초고속 DLL에서 임의의 replica delay에 적응하는 lock 획득을 위한 회로기법)

  • 이지행;조용기;진수종;이주애;김대정;민경식;김동명
    • Proceedings of the IEEK Conference
    • /
    • 2003.07b
    • /
    • pp.1201-1204
    • /
    • 2003
  • This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.

  • PDF

Design & Implementation of Visualization Simulator for Supporting to Learn on Concurrency Control based on 2PLP (2PLP 기반 병행제어 학습을 지원하는 시각화 시뮬레이터의 설계 및 구현)

  • Han, Sang-Hun;Jang, Hong-Jun;Jung, Soon-Young
    • The Journal of Korean Association of Computer Education
    • /
    • v.11 no.4
    • /
    • pp.71-83
    • /
    • 2008
  • The recent advances of the information technology have motivated lots of research efforts to develop new computer-aided teaching and learning methodologies on various computer science topics, such as data structures, operating system, computer networks, and computer architecture. However, there have been only few studies to educate the database subject although it is one of the most important topics in the computer science. Specifically, among the various issues in the database subject, a learner often suffers to understand the mechanism of the concurrency control and recovery of database transaction in the database because it highly interacts with other functions in the database. Obviously, an intelligent visualization tool can help a learner to understand the process of the concurrency control and the recovery of database transaction. The purpose of this study is to develop an efficient visualization tool which can help users understand the two phase locking protocol (2PLP)-based concurrency control. Specifically, this visualization tool is designed to encourage a users' participation and raise their interest by visualizing the process of transactions and allowing users to specify and manipulate their own transactions.

  • PDF

A Phase-Locked Loop Using Switched-Capacitor Loop Filter (Switched-Capacitor 루프 필터를 이용한 Phase-Locked Loop의 설계)

  • 최근일;이용석
    • Proceedings of the IEEK Conference
    • /
    • 2000.11b
    • /
    • pp.333-336
    • /
    • 2000
  • Modem standard CMOS process technology suffer from so large amount of PVT i.e process, voltage and temperature variation over 30% of its desired value that accurate resistor value is hard to be achieved. A filter using switched-capacitor(SC) circuit has a time constant proportional to relative capacitor area ratio rather than its absolute value. If the PLL's loop filter were made out of SC circuit, there could be much less PVT variation problem. Furthermore, programmability on the loop filter can be achieved In this paper, we present the PLL with SC loop filter. The accuracy provided by SC filter would be helpful to enhance PLL's locking behaviour.

  • PDF

Wheel Slip Control of ABS Using Adaptive Control Method (적응제어 기법을 적용한 ABS의 바퀴 슬립 제어)

  • Choi, Jong-Hwan
    • Journal of the Korean Society of Manufacturing Process Engineers
    • /
    • v.5 no.3
    • /
    • pp.71-79
    • /
    • 2006
  • ABS is a safety device for preventing wheel locking in a sudden baking. Its control methods are classified into three types; deceleration control, wheel slip control and deceleration/acceleration control. The braking force takes the influence of the friction coefficient between road and tire, which in turn depends on the wheel slip as well as road conditions. In this paper, it has been proposed the wheel slip control system to apply the adaptive control method at the ABS. To maintain wheel slip to desired wheel slip, it have been done the linearization and designed the adaptive controller to apply gradient method based on the reference model. It is illustrated by computer simulations that the proposed control system gives good performances and adaptation to parameter variation.

  • PDF

An Experimental Study on Oil Pressure Distribution in the Piston-Cylinder Mechanism (피스톤-실린더 기구에서 오일압력 분포에 관한 실험적 연구)

  • Kim, Yeong-Hwan
    • Journal of the Korean Society of Manufacturing Process Engineers
    • /
    • v.10 no.6
    • /
    • pp.77-82
    • /
    • 2011
  • The piston-cylinder mechanism is widely adopted in the hydraulic machine components. In these cases, the hydrodynamic pressures are generated in the clearance gap between the piston and cylinder under lubrication action of the piston. Under the eccentric and tilted condition of the piston in the cylinder bore, the non-symmetric pressure distributions in the circumferential direction result in lateral forces. When the lateral forces act as increasing the eccentricity and tilting ratios, excessive wear can be result in cylinder and piston which are well known 'hydraulic locking' phenomena. In this paper, the hydrodynamic pressures generated in the clearance are measured using a stationary piston and moving cylinder apparatus. The experimental results showed that the hydrodynamic pressure distributions are highly affected by the speed and eccentricity of the cylinder and the oil viscosity.

The Volar Plating of Fracture of the Coronoid Process - Report of Two Cases - (구상돌기 골절에서 내측 접근법을 통한 전방 금속판 고정술 - 2예 보고 -)

  • Jung, Gu-Hee;Cho, Chul-Hyun;Jang, Jae-Ho;Kim, Jae-Do
    • Clinics in Shoulder and Elbow
    • /
    • v.13 no.2
    • /
    • pp.260-265
    • /
    • 2010
  • Purpose: To report the clinical results of two cases of coronoid process fractures that were treated with volar plating through a medial approach. Materials and Methods: Two fractures of the coronoid process that needed to be fixed were managed with open reduction and internal fixation through a medial approach using 2.4 mm locking compression plates (Compact Hand set$^{(R)}$, Synthes, Switzerland). The patients were followed up for 14 months and 17 months and were evaluated using the Mayo Elbow Performance Score (MEPS). Results: The MEPS was 95 for Case 1 and 100 for Case 2. Active elbow joint motions were $5^{\circ}-120^{\circ}$ (Case 1) and $0^{\circ}-130^{\circ}$ (Case 2). Supination and pronation fully recovered. Conclusion: Satisfactory results can be obtained in cases of coronoid process fractures because volar plating through a medial approach allows sound fixation and early mobilization of the elbow joint.