• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.7
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• pp.1408-1415
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• 2002

In this paper, we investigate the effect and the importance of the accuracy of finite element analysis in the shape optimization based on the finite element method and improve the existing finite element which has inaccuracy in some cases. And then, the shape optimization is performed by using the improved finite element. One of the main stream to improve finite element is the prevention of locking phenomenon. In case of bending dominant problems, finite element solutions cannot be reliable because of shear locking phenomenon. In the process of shape optimization, the mesh distortion is large due to the change of the structure outline. So, we have to raise the accuracy of finite element analysis for the large mesh distortion. We cannot guarantee the accurate result unless the finite element itself is accurate or the finite elements are remeshed. So, we approach to more accurate shape optimization to diminish these inaccuracies by improving the existing finite element. The shape optimization using the modified finite element is applied to a two and three dimensional simple beam. Results show that the modified finite element has improved the optimization results.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.65-70
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• 2008

A novel fast locking dual-loop integer-N phase locked loop(PLL) with adaptive bandwidth scheme is presented. When the PLL is out-of-lock, bandwidth becomes much wider than 1/10 of channel spacing with the wide bandwidth loop. When the PLL is near in-lock, bandwidth becomes narrower than 1/10 of channel spacing with the narrow bandwidth loop. The proposed PLL is designed based on a $0.35{\mu}m$ CMOS process with a 3.3V supply voltage. Simulation results show the fast look time of $50{\mu}s$ for an 80MHz frequency jump in a 200KHz channel spacing PLL with almost 14 times wider bandwidth than the channel spacing.

• Journal of KIISE:Databases
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• v.32 no.1
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• pp.86-99
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• 2005

In this paper, we suggest a system which automatically verifies and tunes transaction processing database applications based on program analysis technology. This system automatically verifies two kinds of transaction processing errors. The first case is the un-closed transaction. In this case, data is not updated as expected or performance of overall system can decrease seriously by locking some database tables until the process terminates. The second case is the miss-use of transaction isolation(inking) level. This causes runtime exception or abnormal termination of the program depending on runtime environment. This system automatically tunes two kinds of inefficient definition of transaction processing which decrease the performance of overall system. The first case happens when opened transaction is closed too late. And the second case happens when transaction isolation level is set too high.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.2
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• pp.339-344
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• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.1429-1433
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• 2004

Recently, a dangerous event occurred at the field industry and mechanical system. At developed by SUNGGOK corp. a R-L clutches of a small and high capacity serves safety device from a variety environment of mechanical system, it permits transmission of driving torque form input to output shaft in both directions of rotation, but restrains any feedback torque of the driven load from rotating the output shaft in either direction. This study was carried out to demonstrate through finite element methode and durability estimation for safety of the R-L clutches without sliding during the engagement process. As results, we organized about endurance test methode when applied rated torque.

• ETRI Journal
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• v.29 no.4
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• pp.463-469
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• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• Proceedings of the KSME Conference
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• 2001.11a
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• pp.367-371
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• 2001

In the shape optimization based on the finite element method, the accuracy of finite element analysis of a given structure is important to determine the final shape. In case of a bending dominant problem, finite element solutions by the full integration scheme are not reliable because of the locking phenomenon. Furthermore, in the process of shape optimization, the mesh distortion is large due to the change of the structure outline: therefore, we cannot guarantee the accurate result unless the finite element itself is accurate. We approach to more accurate shape optimization to diminish these inaccuracies by improving the existing finite element. The shape optimization using the modified finite element is applied to a two-dimensional simple beam. Results show that the modified finite element have improved the optimization results.

• Design & Manufacturing
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• v.10 no.1
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• pp.1-6
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• 2016

In this study, the modification structure design of insulation displacement connector developed was considered for simplification of assembly process. The modified connector consisted terminal, wafer and fitting nails. The separation behavior under locking condition for pitch 1.25mm wire to board connector was measured and the apparatus for the test was made. The maximum restraining force was measured about 4.5kgf that was bigger value than the specification limit. And the pulling force of a wire was also indicated about 2.3kgf.

• Proceedings of the KIEE Conference
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• 2000.07d
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• pp.3097-3099
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• 2000

In this paper, we design PLL for a low jitter and fast locking time that is used a new simple precharged CMOS phase frequency detector(PFD). The proposed PFD has a simple structure with using only 18 transistors. Futhermore, the PFD has a dead zone 25ps in the phase characteristic which is important in low jitter applications. The phase and frequency error detection range is not limited as the case of other precharge type PFDs. the simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD. the PLL using the new PED is designed using 0.25${\mu}m$ CMOS technology with 2.5V supply voltage.