• Korean Journal of Applied Biomechanics
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• v.25 no.2
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• pp.157-165
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• 2015

Object : The goals of this research were to make Performance Enhanced Model(PE) taken the largest performance index (PI) through artificial variation of principle components calculated by principle component analysis for trial data, and to verify the effect through comparing kinematic factors between trial data (Raw) and PE. Method : Ten subjects (5 men, 5 women) were recruited and 80% of their maximal record was considered. The PI is a regression equation. In order to develop PE, we extracted Principle components from trial position data (by Principle Components Analysis (PCA)). Before PCA, we made 17 position data to 3 row matrix according to components. We calculated 3 eigen value (principle components) through PCA. And except Y (medial-lateral direction) component (because motion of Y component is small), principle components of X (anterior-posterior direction) and Z (vertical direction) components were changed as following. Changed principle components = principle components + principle components ${\times}$ k. After changing the each principle component, we reconstructed position data using the changed principle components and calculated performance index (PI). A Paired t-test was used to compare Raw data and Performance Enhanced Model data. The level of statistical significance was set at $p{\leq}0.05$. Result : The PI was significantly increased about 12.9kg at PE ($101.92{\pm}6.25$) when compared to the Raw data ($91.29{\pm}7.10$). It means that performance can be increased by optimizing 3D positions. The difference of kinematic factors as follows : the movement distance of the bar from start to lock out was significantly larger (about 1cm) for PE, the width of anterior-posterior bar position in full phase was significantly wider (about 1.3cm) for PE and the horizontal displacement toward the weightlifter after beginning of descent from maximal height was significantly greater (about 0.4cm) for PE. Additionally, the minimum knee angle in the 2-pull phase was significantly smaller (approximately 2.7cm) for the PE compared to that of the Raw. PE was decided at proximal position from the Raw (origin point (0,0)) of PC variation). Conclusion : PI was decided at proximal position from the Raw (origin point (0,0)) of PC variation). This means that Performance Enhanced Model was decided by similar motion to the Raw without a great change. Therefore, weightlifters could be accept Performance Enhanced Model easily, comfortably and without large stress. The Performance Enhance Model can provide training direction for athletes to improve their weightlifting records.

• The Journal of the Korea Contents Association
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• v.20 no.8
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• pp.368-374
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• 2020

Journaling file systems (JFS) manage changes of file systems not yet committed in a data structure known as a journal to restore the file system in the event of an unexpected failure. Extra write operations required for journaling negatively affect the performance of JFS. The high-performance and byte-addressable non-volatile memory (NVM) was expected to easily mitigate these performance problems by providing NVM space as journal storage. However, even with such non-volatile memory technologies, performance problems still arise due to scalability problems inherent in processing transactions of JFS. To solve this problem, we proposes a technique for processing file system transactions for scalable performance. To this end, lock-free data structures are used and multiple I/O requests are allowed to simultaneously be processed on high-performance storage devices with multiple I/O channels. We evaluate the file system with the proposed technique by comparing the original ext4 file system and the recent proposed NVM-based journaling file system on a multi-core server, and experimental results show that our file system has better performance (up-to 2.9/2.3 times) than the original ext4 file system and the recent NVM-based journaling file system, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.31 no.1
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• pp.41-48
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• 2008

Enhanced machine reliability has dramatically reduced the rate and number of railway accidents but for further reduction human error should be considered together that accounts for about 20% of the accidents. Therefore, the objective of this study was to suggest a new taxonomy of performance shaping factors (PSFs) that could be utilized to identify the causes of a human error associated with railway accidents. Four categories of human factor, task factor, environment factor, and organization factor and 14 sub-categories of physical state, psychological state, knowledge/experience/ability, information/communication, regulation/procedure, specific character of task, infrastructure, device/MMI, working environment, external environment, education, direction/management, system/atmosphere, and welfare/opportunity along with 131 specific factors was suggested by carefully reviewing 8 representative published taxonomy of Casualty Analysis Methodology for Maritime Operations (CASMET), Cognitive Reliability and Error Analysis Method (CREAM), Human Factors Analysis and Classification System (HFACS), Integrated Safety Investigation Methodology (ISIM), Korea-Human Performance Enhancement System (K-HPES), Rail safety and Standards Board (RSSB), $TapRoot^{(R)}$, and Technique for Retrospective and Predictive Analysis of Cognitive Errors (TRACEr). Then these were applied to the case of the railway accident occurred between Komo and Kyungsan stations in 2003 for verification. Both cause decision chart and why-because tree were developed and modified to aid the analyst to find causal factors from the suggested taxonomy. The taxonomy was well suited so that eight causes were found to explain the driver's error in the accident. The taxonomy of PSFs suggested in this study could cover from latent factors to direct causes of human errors related with railway accidents with systematic categorization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.7-14
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• 2008

In this paper, we designed the HVIC(High Voltage Gate Driver IC) which has improved noise immunity characteristics and high driving capability. Operating frequency and input voltage range of the designed HVIC is up to 500kHz and 650V, respectively. Noise protection and schmitt trigger circuit is included in the high-side level shifter of designed IC which has very high dv/dt noise immunity characteristic(up to 50V/ns). And also, rower dissipation of high-side level shifter with designed short-pulse generation circuit decreased more that 40% compare with conventional circuit. In addition, designed HVIC includes protection and UVLO circuit to prevent cross-conduction of power switch and sense power supply voltage of driving section, respectively. Protection and UVLO circuit can improve the stability of the designed HVIC. Spectre and Pspice circuit simulator were used to verify the operating characteristics of the designed HVIC.

• Journal of The Korean Association For Science Education
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• v.21 no.1
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• pp.76-88
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• 2001

This study explored people's accuracy and methods of estimating some base physical quantities, i.e. length, mass, time and temperature. A total of 40 members, ranging from freshmen to professors, of a physics education department of a local university were asked to make two different kinds of estimations, intuitive and operational, on two sets of objects. For intuitive estimation, they were asked to make estimations on four given objects (length - wood chopsticks, mass - rubber eraser, time electric fan, temperature - water in a cup) as soon as they faced with the objects, usually within a few seconds of seeing. For operational estimation, they were allowed to make estimations on a different set of objects (length - plastic rod, mass - lock, time - simple pendulum, temperature - water in a cup) with enough time and they could apply various available methods (e.g. using pencil to estimate the object's length, counting their own pulse rate to estimate time) for the estimation. The findings of this study can be summarized as follows: (1) for length, mass and temperature the intuitive estimations were better performed while for the time estimation the result was the reverse; (2) there was no positive relationship between the amount of physics experience and the accuracy of the estimation; (3) in general, people's accuracy of the length estimation was best performed while their mass estimation was worst performed; (4) people used their own various methods for estimation, esp. using nearby objects around them and applying mental units which have convenient values (e.g. 30cm, 50cm, 1kg, 1 Keun, 1 second).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.1
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• pp.30-43
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• 2008

Memory reference instructions such as loads or stores are critical factors that limit the processing power of processor. The prefetching technique is an effective way to reduce the latency caused from memory access. However, excessively aggressive prefetch leads to cache pollution so as to cancel out the advantage of prefetch. In this study, four filtering schemes have been compared and evaluated which dynamically decide whether to begin prefetch after referring a filtering table to decrease cache pollution. First, A bi-states scheme has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete state scheme has been introduced to be used as a reference for the comparative study. A block address lookup scheme has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the bi-states scheme, the contents of each entry have the fields the same as the complete state scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. Experimental results from commonly used general benchmarks and multimedia programs show that average cache miss ratio have been decreased by 10.5% for the block address lookup scheme(BAL) compare to conventional dynamic filter scheme(2-bitSC).

• Proceedings of the Korean Society of Community Living Science Conference
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• 2009.09a
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• pp.84-84
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• 2009

농촌관광은 농촌마을을 중심으로 활성화가 되어야하며 이를 매개로 하여 농촌주민의 농외 소득증대와 더불어 농촌 삶의 질을 높일 수 있다. 최근에 이르러 농촌관광의 성패는 그 마을이 가진 잠재적 어메니티 자원뿐만 아니라 이러한 잠재자원을 활용하여 마을을 성공적으로 운영할 인적자원이 보다 중요한 요인으로 인식되고 있다. 이에 본 연구에서는 농촌관광마을의 해설 및 체험지도 인력을 대상으로 활동특성 현황을 파악하고자 마을단위로 조사하여 분석하였다. 정부가 지원한 마을 중 가장 많은 부분을 차지하는 녹색농촌체험마을(농림수산식품부), 농촌전통테마마을(농촌진흥청)은 2009년까지 총 612개소이나 이 중 인력기반이 형성되었을 것으로 판단되는 2007년까지 선정된 농촌관광마을 403개 중 100개 마을을 무작위로 선정하였다. 조사대상은 마을의 추진위원장 중심으로 리더 100명, 추진위원장 추천의 마을해설 및 체험지도 인력 명단에서 2~4명 정도, 총 300명을 자기기입식 및 직접면접 조사를 병행하여 조사 분석하였다. 해설 및 체험지도자 활용유형을 생태해설, 생활문화, 농업기술, 전통놀이/문화, 전통 음식, 전통공예, 지역설화로 분류하였으며, 지도방법은 직접시현(체험)과 간접시현(안내/해설)으로 구분하여 분석을 실시하였다. 마을에서 활동하고 있는 체험지도 인력은 평균 6.6명이었고, 마을해설에 참여하는 내부인력은 평균 3.2명, 외부인력은 0.8명이었으며, 체험지도에 참여하는 내부인력은 평균 4.2명, 외부인력은 1명으로 나타나 마을해설보다는 체험지도에 외부인력을 더 활용하는 것으로 나타났다. 이렇게 마을에서 활동하고 있는 해설 및 체험지도인력들에 대해 농촌관광마을 리더들은 부족하다는 의견이 49%로 과반수 정도를 차지하여 농촌체험지도를 위한 인력이 부족하다고 판단하는 것으로 나타났다. 마을해설이나 체험지도에 참여하는 사람들의 체험지도 형태는 주로 새로운 지식을 스스로 공부하여 해설하는 경우가 45.5%, 전문화된 개설이 가능한 비율이 19.9%, 안내만 함 19.5%, 시연만 함 15.2%로서 대부분이 지도인력들이 스스로 해설에 적극적으로 참여하고 있었다. 또한 체험거리 한두 가지를 전문적으로 지도하는 비율(41.2%)보다 여러 가지를 종합적으로 지도하는 비율이 58.8%로 높게 나타나 한 사람이 몇 가지를 동시에 담당하여 지도하는 체험지도에 대한 전문성 확보가 미흡한 것으로 보인다. 이와 같이 본 연구에서 농촌관광마을의 인적자원 활용 현황을 살펴보고, 마을 해설사의 인적자원의 잠재성을 활용 농촌마을의 발전 동력을 찾고자 함에 연구에 의의가 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.