• Title/Summary/Keyword: Location memory

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WAP-LRU: Write Pattern Analysis Based Hybrid Disk Buffer Management in Flash Storage Systems (WAP-LRU : 플래시 스토리지 시스템에서 쓰기 패턴 분석 기반의 하이브리드 디스크 버퍼 관리 기법)

  • Kim, Kyung Min;Choi, Jun-Hyeong;Kwak, Jong Wook
    • IEMEK Journal of Embedded Systems and Applications
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    • v.13 no.3
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    • pp.151-160
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    • 2018
  • NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

Location Based Routing Service In Distributed Web Environment

  • Kim, Do-Hyun;Jang, Byung-Tae
    • Proceedings of the KSRS Conference
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    • 2003.11a
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    • pp.340-342
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    • 2003
  • Location based services based on positions of moving objects are expanding the business area gradually. The location is included all estimate position of the future as well as the position of the present and the past. Location based routing service is active business application in which the position information of moving objects is applied efficiently. This service includes the trajectory of past positions, the real-time tracing of present position of special moving objects, and the shortest and optimized paths combined with map information. In this paper, we describes the location based routing services is extend in distributed web GIS environment. Web GIS service systems provide the various GIS services of analyzing and displaying the spatial data with friendly user - interface. That is, we propose the efficient architecture and technologies for servicing the location based routing services in distributed web GIS environment. The position of moving objects is acquired by GPS (Global Positioning System) and converted the coordinate of real world by map matching with geometric information. We suppose the swapping method between main memory and storages to access the quite a number of moving objects. And, the result of location based routing services is wrapped the web-styled data format. We design the schema based on the GML. We design these services as components were developed in object-oriented computing environment, and provide the interoperability, language-independent, easy developing environment as well as re - usability.

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Performance Enhancement Architecture for HLR System Based on Distributed Mobile Embedded System (분산 모바일 임베디드 시스템 기반의 새로운 위치정보 관리 시스템)

  • Kim Jang Hwan
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.12B
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    • pp.1022-1036
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    • 2004
  • In mobile cellular network the ever-changing location of a mobile host necessitates the continuous tracking of its current position and efficient management of location information. A database called Home Location Register(HLR) plays a major role in location management in this distributed environment, providing table management, index management, and backup management facilities. The objectives of this paper are to identify the p개blems of the current HLR system through rigorous analysis, to suggest solutions to them, and to propose a new architecture for the HLR system. In the HLR system, a main memory database system is used to provide real-time accesses and updates of subscriber's information. Thus it is suggested that the improvement bemade to support better real-time facilities, to manage subscriber's information more reliably, and to accommodate more subscribers. In this paper, I propose an efficient backup method that takes into account the characteristics of HLR database transactions. The retrieval speed and the memory usage of the two-level index method are better than those of the T-tree index method. Insertion md deletion overhead of the chained bucket hashing method is less than that of modified linear hashing method. In the proposed backup method, I use two kinds of dirty flags in order to solve the performance degradation problem caused by frequent registration-location operations. Performance analysis has been performed to evaluate the proposed techniques based on a system with subscribers. The results show that, in comparison with the current techniques, the memory requirement is reduced by more than 62%,directory operations, and backup operation by more than 80%.

The role of positive affect in virtual collaboration: a transactive memory system perspective

  • Chae, Seong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.5
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    • pp.99-109
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    • 2016
  • Creative performance has been regarded as the key to the success of an organization in recent years, and is considered essential for the survival of an organization. Organizations must find and develop creative solutions to deal with a variety of business issues. How can organizations become more creative? To develop creativity, organizations must make it easier to connect the knowledge and perspectives of its various members, who may be scattered around the world, by developing a virtual team. Drawing from the transactive memory systems (TMS), which include expertise location, credibility, and coordination, this study investigates how the positive affect of team members influences the development of creative performance during virtual collaboration where face-to-face team activities are limited. The proposed structured model was empirically tested with cross-sectional data from 322 individuals. Results indicated that the positive affect of team members was found to moderate the relationship between TMS and creativity. Through this study, we expect to provide an understanding of the mechanisms involved in developing creativity among team members in a virtual work environment.

Dynamic behavior of a seven century historical monument reinforced by shape memory alloy wires

  • Hamdaoui, Karim;Benadla, Zahira;Chitaoui, Houssameddine;Benallal, Mohammed Elamine
    • Smart Structures and Systems
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    • v.23 no.4
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    • pp.337-345
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    • 2019
  • This work resumes a research that proposes the use of the technique based on the dissipation energy of the shape memory alloy (SMA) ties. It focuses principally on the assessment of the effectiveness of the use of these smart materials on displacements, accelerations and the stresses of the minaret of the great mosque of Ajloun in Jordan. The 3-D finite element model of the minaret is performed by the ANSYS software. First of all, the proposed model is calibrated and validated according to the experimental results gathered from ambient vibration testing results. Then, a nonlinear transient analysis is considered, when the El-Centro earthquake is used as the input signal. Different simulating cases concerning the location, number and type of SMA devices are proposed in order to see their influence on the seismic response of the minaret. Hence, the results confirm the effectiveness of the proposed SMA device.

Object-Size and Call-Site Tracing based Shared Memory Allocator for False Sharing Reduction in DSM Systems (분산 공유 메모리 시스템에서 거짓 공유를 줄이는 객체-크기 및 호출지-추적 기반 공유 메모리 할당 기법)

  • Lee, Jong-Woo;Park, Young-Ho;Yoon, Yong-Ik
    • Journal of Digital Contents Society
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    • v.9 no.1
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    • pp.77-86
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    • 2008
  • False sharing is a result of co-location of unrelated data in the same unit of memory coherency, and is one source of unnecessary overhead being of no help to keep the memory coherency in multiprocessor systems. Moreover, the damage caused by false sharing becomes large in proportion to the granularity of memory coherency. To reduce false sharing in page-based DSM systems, it is necessary to allocate unrelated data objects that have different access patterns into the separate shared pages. In this paper we propose sized and call-site tracing-based shared memory allocator, shortly SCSTallocator. SCSTallocator places each data object requested from the different call-sites into the separate shared pages, and at the same time places each data object that has different size into different shared pages. Consequently data objects that have the different call-site and different object size prohibited from being allocated to the same shared page. Our observations show that our SCSTallocator outperforms the existing dynamic shared memory allocators. By combining the two existing allocation technique, we can reduce a considerable amount of false sharing misses.

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The Effects of Korean Lexical Characteristics on Memory Span (한국어 어휘특성들이 기억폭에 미치는 효과)

  • Park Tae-Jin;Park Sun-Hee;Kim Tae-Ho
    • Korean Journal of Cognitive Science
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    • v.17 no.1
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    • pp.15-27
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    • 2006
  • The effects of the number of Hangul syllable, the nunber/location of batchim in a Hangul word, and compound/noncompound Hangul word on memory span were examined. The results were that (1) the more syllables a word had, the lower us memory span was, (2) the more batchims a two-syllable word had, the lower its memory span was (Korean batchim effect on memory span), (3) noncompound word had higher memory span than compound word. The reading speed of above mentioned words was measured and the results were that (1) the more syllables a word had, the slower its reading speed was, (2) but the reading speed of a two-syllable word was forest when it had a batchim on second syllable than when it had no batchim or had a batchim on first syllable or batchims on both syllables (Korean ending batchim effect on reading speed), (3) noncompound word was read faster thu compound word. Korean ending batchim effect on reading speed was not compatible with the explanation by articulatory loop bur compatible with the explanation by visual cache where the orthographic information was represented. The results suggest that memory span was influenced nor only by phonological information but also by orthographic information.

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Selecting the Optimal Loading Location through Prediction of Required Amount for Goods based on Bi-LSTM (Bi-LSTM 기반 물품 소요량 예측을 통한 최적의 적재 위치 선정)

  • Sein Jang;Yeojin Kim;Geuntae Kim;Jonghwan Lee
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.3
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    • pp.41-45
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    • 2023
  • Currently, the method of loading items in the warehouse, the worker directly decides the loading location, and the most used method is to load the product at the location closest to the entrance. This can be effective when there is no difference in the required amount for goods, but when there is a difference in the required amount for goods, it is inefficient because items with a small required amount are loaded near the entrance and occupy the corresponding space for a long time. Therefore, in order to minimize the release time of goods, it is essential to select an appropriate location when loading goods. In this study, a method for determining the loading location by predicting the required amount of goods was studied to select the optimal loading location. Deep learning based bidirectional long-term memory networks (Bi-LSTM) was used to predict the required amount for goods. This study compares and analyzes the release time of goods in the conventional method of loading close to the entrance and in the loading method using the required amount for goods using the Bi-LSTM model.

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Three-Dimensional Stacked Memory System for Defect Tolerance (적층 구조의 3차원 결함극복 메모리)

  • Han, Se-hwan;You, Young-Gap;Cho, Tae-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.11
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    • pp.23-29
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    • 2010
  • This paper presents a method for constructing a memory system using defective memory chips comprising faulty storage blocks. The three-dimensional memory system introduced here employs a die-stacked structure of faulty memory chips. Signals lines passing through the through-silicon-vias (TSVs) connect chips in the defect tolerant structure. Defective chips are classified into several groups each group comprising defective chips having faulty blocks at the same location. A defect tolerant memory system is constructed using chips from different groups. Defect-free storage blocks from spare chips replace faulty blocks using additional routing circuitry. The number of spare chips for defect tolerance is $s={\ulcorner}(k{\times}n)/(m-k){\urcorner}$ to make a system defect tolerant for (n+s) chips with k faulty blocks among m independently addressable blocks.

Thermal Performance Analysis for Cu Block and Dense Via-cluster Design of Organic Substrate in Package-On-Package

  • Lim, HoJeong;Jung, GyuIk;Kim, JiHyun;Fuentes, Ruben
    • Journal of the Microelectronics and Packaging Society
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    • v.24 no.4
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    • pp.91-95
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    • 2017
  • Package-On-Package (PoP) technology is developing toward smaller form factors with high-speed data transfer capabilities to cope with high DDR4x memory capacity. The common application processor (AP) used for PoP devices in smartphones has the bottom package as logic and the top package as memory, which requires both thermally and electrically enhanced functions. Therefore, it is imperative that PoP designs consider both thermal and power distribution network (PDN) issues. Stacked packages have poorer thermal dissipation than single packages. Since the bottom package usually has higher power consumption than the top package, the bottom package impacts the thermal budget of the top package (memory). This paper investigates the thermal and electrical characteristics of PoP designs, particularly the bottom package. Findings include that via and dense via-cluster volume have an important role to lower thermal resistance to the motherboard, which can be an effective way to manage chip hot spots and reduce the thermal impact on the memory package. A Cu block and dense via-cluster layout with an optimal location are proposed to drain the heat from the chip hot spots to motherboard which will enhance thermal and electrical performance at the design stage. The analytical thermal results can be used for design guidelines in 3D packaging.