• Journal of the Korean Society for Precision Engineering
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• v.19 no.1
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• pp.99-106
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• 2002

For the development of a ultra-precision CNC polishing system including on-machine measurement system, we study a corrective polishing algorithm. We calculated unit removal profiles for various flat type polishing tools and polishing tool positions. Using these results we simulate the corrective polishing process based on dwell time control. We calculate dwell time distributions and residual error of the polishing simulation method and the FFT calculation method. We test corrective polishing algorithm with an optical glass. The target removal shape is a sine wave that has amplitude 0.3 micro meters. We find this polishing process has a machining resolution of nanometer order and is effective for sub-micrometer order machining. This result will be used for the software development of the CNC polishing system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.950-955
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• 2001

For the development of an ultra-precision CNC polishing system including on-machine measurement system, we study a corrective polishing algorithm. We analyze and test the unit removal profiles for a ball type polishing tool. Using these results we calculate dwell time distributions and residual errors for a target removal shape. We use the polishing simulation method and feed rate calculation method for the dwell time calculation. We test corrective polishing algorithm with an optical glass. The target removal shape is a sine wave that has amplitude 0.3 micro meters. We find this polishing process has a machining resolution of nanometer order and is effective for sub-micrometer order machining. This result will be used for the software development of the CNC polishing system.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.11a
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• pp.783-786
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• 2000

For the development of a ultra-precision CMC polishing system including on-machine measurement system, we study a corrective polishing algorithm. We calculated unit removal profiles for various polishing tools and polishing tool positions. Using these results we simulate the corrective polishing process based on dwell time control. We calculate dwell time distributions and residual error of the polishing simulation method and the FFT calculation method. We got good dwell time distributions and small residual when we used the FFT calculation method. This results will be used for the optimization of corrective polishing process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.525-526
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• 2007

Over-polishing is required to completely remove the material of top surface across whole wafer, in spite of a local dishing problem. This paper introduces the two-step CMP process using protective layer and high selectivity slurry, to reduce dishing amount and variation. The 30nm thick protective oxide layer was deposited on the pattern, and then polished with low selectivity slurry to partially remove the projected area while suppressing the removal rate of the recessed area. After the first step CMP process, high selectivity slurry was used to minimize the dishing amount and variation in pattern structure. Experimental result shows that two-step CMP process can be successfully applicable to reduce the dishing defect generated in over-polishing.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.9
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• pp.5460-5466
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• 2014

In this study, mainly for kitchen knives and small swords, cutlery, etc. STS420J2 used material used for the experiments. In order to cure the surface of the test piece after the rough grinding and fine grinding was performed in order polishing. Perform the surface hardening of STS420J2 local area by using a diode laser. The output of the laser diode and the feed rate to the process variable. Micro-hardness testing, microstructure testing, scanning electron microscope testing(SEM), the heat input to the analysis. After analyzing the experiment to compare the mechanical properties of the material. When using a diode laser to assess the soundness of the surface hardening. Accordingly, the process for deriving the optimum demonstrate the feasibility.