• Journal of KIISE:Computer Systems and Theory
• /
• v.32 no.10
• /
• pp.520-529
• /
• 2005

A feature-based 3D modeling algorithm is presented in this paper. Since conventional methods use depth-based techniques, they need much time for the image matching to extract depth information. Even feature-based methods have less computation load than that of depth-based ones, the calculation of modeling error about whole pixels within a triangle is needed in feature-based algorithms. It also increase the computation time. Therefore, the proposed algorithm consists of three phases, which are an initial 3D model generation, model evaluation, and model refinement phases, in order to acquire an efficient 3D model. Intensity gradients and incremental Delaunay triangulation are used in the Initial model generation. In this phase, a morphological edge operator is adopted for a fast edge filtering, and the incremental Delaunay triangulation is modified to decrease the computation time by avoiding the calculation errors of whole pixels and selecting a vertex at the near of the centroid within the previous triangle. After the model generation, sparse vertices are matched, then the faces are evaluated with the size, approximation error, and disparity fluctuation of the face in evaluation stage. Thereafter, the faces which have a large error are selectively refined into smaller faces. Experimental results showed that the proposed algorithm could acquire an adaptive model with less modeling errors for both smooth and abrupt areas and could remarkably reduce the model acquisition time.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11A
• /
• pp.902-911
• /
• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.10 no.8
• /
• pp.3551-3567
• /
• 2016

The Low Earth Orbit satellite network has the unique characteristics of the non-uniform and time-variant traffic load distribution, which often causes severe link congestion and thus results in poor performance for delay-sensitive flows, especially when the network is heavily loaded. To solve this problem, a novel adaptive routing algorithm, referred to as the delay-oriented adaptive routing algorithm (DOAR), is proposed. Different from current reactive schemes, DOAR employs Destination-Sequenced Distance-Vector (DSDV) routing algorithm, which is a proactive scheme. DSDV is extended to a multipath QoS version to generate alternative routes in active with real-time delay metric, which leads to two significant advantages. First, the flows can be timely and accurately detected for route adjustment. Second, it enables fast, flexible, and optimized QoS matching between the alternative routes and adjustment requiring flows and meanwhile avoids delay growth caused by increased hop number and diffused congestion range. In addition, a retrospective route adjustment requesting scheme is designed in DOAR to enlarge the alternative routes set in the severe congestion state in a large area. Simulation result suggests that DOAR performs better than typical adaptive routing algorithms in terms of the throughput and the delay in a variety of traffic intensity.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.1
• /
• pp.13-20
• /
• 2015

Existing LDMOS power amplifier that used class-AB and doherty system shows 55% of efficiency in 60MHz narrow band. Because RRH has been applied to power amplifier at base station. It is required that over 100MHz expanded band and more than 60% high efficiency power amplifier. In this paper we designed class-J power amplifier using LDMOS FET which has over 60% high efficiency characteristic in 200MHz. The output matching circuit of designed class-J power amplifier has been optimized to contain pure reactance at second harmonic load and has low quality factor Q. As a measurement result of the amplifier, when we input continuous wave signal, we checked 62~70% of power added efficiency(PAE) in 2.06~2.2GHz including WCDMA frequency as a 10W class-J power amplifier.

• International Journal of Naval Architecture and Ocean Engineering
• /
• v.9 no.3
• /
• pp.315-325
• /
• 2017

The design dimension may not be satisfactory at the final stage due to the welding during the assembly stage, leading to cutting or adding the components in large structure constructions. The productivity is depend on accuracy of the welding quality especially at assembly stage. Therefore, it is of utmost importance to decide the component dimension during each assembly stage considering the above situations during the designing stage by exactly predicting welding deformation before the welding is done. Further, if the system that predicts whether welding deformation is equipped, it is possible to take measures to reduce deformation through FE analysis, helping in saving time for correcting work by arresting the parts which are prone to having welding deformation. For the FE analysis to predict the deformation of a large steel structure, calculation time, modeling, constraints in each assembly stage and critical welding length have to be considered. In case of fillet welding deformation, around 300 mm is sufficient as a critical welding length of the specimen as proposed by the existing researches. However, the critical length in case of butt welding is around 1000 mm, which is far longer than that suggested in the existing researches. For the external constraint, which occurs as the geometry of structure is changed according to the assembly stage, constraint factor is drawn from the elastic FE analysis and test results, and the magnitude of equivalent force according to constraint is decided. The comparison study for the elastic FE analysis result and measurement for the large steel structure based on the above results reveals that the analysis results are in the range of 80-118% against measurement values, both matching each other well. Further, the deformation of fillet welding in the main plate among the total block occupies 66-89%, making welding deformation in the main plate far larger than the welding deformation in the longitudinal and transverse girders.

• International Journal of Aeronautical and Space Sciences
• /
• v.10 no.2
• /
• pp.86-94
• /
• 2009

This paper deals with the creation of a new, low-cost point/position tracking system that can measure deformations in engineering structures with simple commercially widespread cameras. Though point tracking systems do exist today, such as Stereo Pattern Recognition (SPR) and Projection Moir$\acute{e}$ Interferometry (PMI) systems, they are far too costly to use to analyze small, simple structures because complex optical components such as large flashes, high-resolution cameras and data acquisition systems with several computers are required. We developed a point tracking system using commercial cameras. This system used IR LEDs and commercial IR CCD cameras to minimize the interference posed by other extraneous light sources. The main algorithm used for this system is an optical point tracking algorithm, which is composed of the point extraction algorithm and the point matching algorithm for 3-D motion estimation. a series of verification tests were performed. Then, the developed point tracking system was applied to measure deformations of an acrylic plate under a mechanical load. The measured deformations of the acrylic plate matched well with the numerical analysis results. The results indicate that the developed point tracking system is reliable enough to measure continuous deformed shapes of various engineering structures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.22 no.1
• /
• pp.76-80
• /
• 2011

This paper has proposed a 3~5 GHz low-power and wideband LNA(Low Noise Amplifier), which has been implemented in a 0.18-${\mu}m$ CMOS technology. The proposed LNA has basically the noise-cancelling topology to achieve a balun-function, wideband input matching, and relative low noise figure. In addition, it has utilized a 2nd-order LC-band-pass filter(BPF) as its output load to achieve higher power gain and lower noise figure with the lowest dc power consumption among previously reported works. The proposed amplifier consumes only 3.94 mA from a 1.8 V supply voltage. The simulation results show a power gain of more than +17 dB, a noise figure of less than +4 dB, and an input IP3 of -15.5 dBm.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.11
• /
• pp.2479-2485
• /
• 2013

In this paper, we present a design for solid-state radar SSPA with sequential bias. We apply to variable extension pulse generator to eliminate signal distortion which is caused by bias rising/falling delay of power amplifier. There is an optimum impedance matching circuit to have high efficiency of GaN-power device by measuring microwave characteristics through load-pull method. The designed SSPA is consisted of pre-amplifier, drive-amplifier and main-amplifier as a three stages to apply for X-Band solid-state radar. Thereby we made a 200W SSPA which has output pulse maximum power shows 53.67dBm and its average power is 52.85dBm. The optimum design of transceiver module for solid-state pulse compression radar which is presented in this dissertation, it can be available to miniaturize and to improve the radar performances through additional research for digital radar from now on.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.16 no.9
• /
• pp.862-876
• /
• 1991

In this theses, the procedure for finding the equivalent immittance of an n-line coupled structures is presented in terms of the normal mode parameters of the n-line coupled system. The above generalized equations can be applied to the various Coupled structures including directional couplers, DC blocks, bandpass/band elimination filters, and various other uniformly coupled filters. The design equations are based on a simplified TEM(Quasi TEM) mode. The obtained results and the definition of the scattering parameters for a general coupled line four port with arbitrary terminations are used to present the procedure to determine the optimum physical dimensions matching the given load impedances connected to input, output port. Multiple coupled rnicrostrip two-port with three lines circuit designed shows little discrepancy between the conventional method and this one. Four port with five lines were fabricated on teflon substrate($e$r=2.55) with its thickness h=l.588mm designed at the center frequency, 4 GHz. Their measured results are fairly close to the ones by computation.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.1
• /
• pp.110-114
• /
• 2008

In this paper, high efficient class F power amplifier with dual band has been realized. Dual band power amplifier have used modify stub matching for single FET, center frequency 2.14GHz and 5.2GHz respectively. Dual band amplifier is 32.65dBm output power, gain 11dB and PAE 36% at the 2.14GHz, 7dB gain at the 5.2GHz. Design of a dual band class F power amplifier using harmonic control circuit. The measured are 9.9dB gain, 30dBm output power and PAE 55% at the 2.14GHz, 11.7dB gain at the 5.2GHz. This paper is being used the load-pull method and it maximizes output power and it is using the only one transistor in the paper. As a result, this research will obtain a dual band high PAE power amplifier.