• Title/Summary/Keyword: Literal Switch

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A New Function Embedding Method for the Multiple-Controlled Unitary Gate based on Literal Switch (리터럴 스위치에 의한 다중제어 유니터리 게이트의 새로운 함수 임베딩 방법)

  • Park, Dong-Young
    • The Journal of the Korea institute of electronic communication sciences
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    • v.12 no.1
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    • pp.101-108
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    • 2017
  • As the quantum gate matrix is a $r^{n+1}{\times}r^{n+1}$ dimension when the radix is r, the number of control state vectors is n, and the number of target state vectors is one, the matrix dimension with increasing n is exponentially increasing. If the number of control state vectors is $2^n$, then the number of $2^n-1$ unit matrix operations preserves the output from the input, and only one can be performed the unitary operation to the target state vector. Therefore, this paper proposes a new method of function embedding that can replace $2^n-1$ times of unit matrix operations with deterministic contribution to matrix dimension by arithmetic power switch of the unitary gate. The proposed function embedding method uses a binary literal switch with a multivalued threshold, so that a general purpose hybrid MCU gate can be realized in a $r{\times}r$ unitary matrix.

A Study on the Design of Binary to Quaternary Converter (2진-4치 변환기 설계에 관한 연구)

  • 한성일;이호경;이종학;김흥수
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.3
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    • pp.152-162
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    • 2003
  • In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.