• Journal of IKEEE
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• v.22 no.2
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• pp.420-426
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• 2018

In the near future, CNTFET(Carbon NanoTube Field Effect Transistor) is considered as one of the most promising candidate for the replacement of modern silicon-based transistors by utilizing the ballistic or near-ballistic transport capability of CNT(Carbon NanoTube). For the large-scale fabrication of high performance CNTFET, semiconducting CNTs have to be well-aligned with a fixed pitch and high densities in the each CNTFET. However, due to the immaturity of the CNTFET fabrication process, CNTs can be unevenly positioned in a CNTFET and existing HSPICE library file cannot support the circuit level evaluation of performance variation caused by the unevenly positioned CNTs. To evaluate the performance variation, linear programming methodology was suggested previously, but the errors can be made during the calculation of the current and the gate capacitance of a CNTFET. In this paper, the reasons causing errors will be discussed in detail and the new methodology to reduce the errors will be also suggested. Simulation results shows that the errors can be reduced from 7.096% to 3.15%.