• The KIPS Transactions:PartC
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• v.16C no.3
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• pp.357-362
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• 2009

Summation generator can be easily made as a simple hardware or software and it's period and linear complexity are very high. So it is appropriate to mobile security system for ubiquitous environment. But it showed us the weakness by Golic's correlation attack and Meier's fast correlation attack. In this paper, we proposed a Nonlinear Summation Generator(NSG), which is improved by using LFSR and NFSR(nonlinear feedback shift register), is different from $E_0$ algorithm which use only LFSR in summation generator. It enhanced nonlinearity and is hard to decipher even though the correlation attack or fast correlation attack. We also analyzed the security aspects and the performances for the proposed algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1702-1708
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• 2007

Dragon Stream Cipher is proposed for software base implementation in the eSTREAM project. Now this stream cipher is selected as a phase 3 focus candidate. Dragon is a new stream cipher contructed using a single word based NIFSR(non-linear feed back shift register) and 128/256 key/IV(Initialization Vector). Dragon is the keystream generator that produce 64bits of keystream. In this paper, we present an implementation of Drag(m stream cipher algorithm in hardware. Finally, the implementation is on Altera FPGA device, EP3C35F672I and the timing simulation is done on Altera's Quartus II. A result of 111MHz maximum clock rate and 7.1Gbps is throughput is obtained from the implementation.

• Convergence Security Journal
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• v.18 no.4
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• pp.27-33
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• 2018

Stream cipher is an one-time-pad type encryption algorithm that encrypt plaintext using simple operation such as XOR with random stream of bits (or characters) as symmetric key and its security depends on the randomness of used stream. Therefore we can design more secure stream cipher algorithm by using mathematical analysis of the stream such as period, linear complexity, non-linearity, correlation-immunity, etc. The key stream in stream cipher is generated in linear feedback shift register(LFSR) having characteristic polynomial. The primitive polynomial is the characteristic polynomial which has the best security property. It is used widely not only in stream cipher but also in SEED, a block cipher using 8-degree primitive polynomial, and in Chor-Rivest(CR) cipher, a public-key cryptosystem using 24-degree primitive polynomial. In this paper we present the concept and various properties of primitive polynomials in Galois field and prove the theorem finding the number of irreducible polynomials and primitive polynomials over $F_p$ when p is larger than 2. This kind of research can be the foundation of finding primitive polynomials of higher security and developing new cipher algorithms using them.

• Proceedings of the Korea Multimedia Society Conference
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• 2001.11a
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• pp.681-685
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• 2001

본 논문에서는 난수 발생기로써 랜덤성이 우수하고 하드웨어 설계시 고속성이 보장되어 LFSR(Linear Feedback Shift register) 대안으로 소개되고 있는 셀룰라 오토마타(CA: Cellular Automata)를 소개하고 이를 이용한 새로운 블록 암호 알고리즘을 제안한다. 제안된 블록 암호 알고리즘은 Fiestel 구조로써 라운드 함수와 키 스케쥴링 모두를 셀룰러 오토마타를 이용하여 구성함으로써 구현의 편이성과 고속성을 추구하였다. 제안 알고리즘에 대한 간단한 통계적 검정과 성능평가를 통해 기존 표준 알고리즘고의 비교를 수행하였다.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.533-536
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• 2003

본 논문에서는 전화선을 이용한 고속 홈네트워크인 HomePNA 2.0 시스템에서 HomePNA 2.0 (H2) 프레임을 만들기 위한 프레임 프로세싱 중, 다항식 나누기 연산을 통한 CRC (Cyclic Redundancy Check) 16비트 생성, HCS (Header Check Sequence) 8비트 생성 및 혼화(Scrambling) 처리에 있어서 입력 8 비트를 동시에 병렬 처리함으로써 기존의 1 비트 입력을 LFSR (Linear Feedback Shift Register)를 사용한 다항식 나누기 연산을 수행했을 때보다 빠른 속도로 H2 프레임을 구현하고자 하는 고속 처리 기법을 제시하고 이의 성능을 검증하였다.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.07a
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• pp.33-36
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• 2003

본 논문에서는 GF(2$^{m}$ ) 상에서 효율적인 공간 복잡도를 가진 LFSR(Linear Feedback Shift Register) 구조 기반의 모듈러 곱셈기를 제안한다. 제안된 구조는 기약다항식으로 모든 계수가 1인 속성의 AOP(All One Polynomial)를 이용한다. 제안된 구조는 구조복잡도 면에서 기존의 구조들보다 훨씬 효율적이다. 제안된 곱셈기는 공개키 암호의 기본 구조로 사용될 수 있다.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.85-88
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• 2002

In this paper, the proposed watermark algorithm is based on energy distribution of the subband coefficients in the frequency domain and edge of the original image in the spacial domain. Out of these information, the KeyMap which decides the embedded position of watermark is produced. And then the binary watermark is embedded into the wavelet coefficient of LL3 subband using KeyMap and LFSR(Linear Feedback Shift Register).

• Journal of Korea Society of Industrial Information Systems
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• v.9 no.1
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• pp.43-48
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• 2004

This paper presents new architectures based on the linear feedback shia resister architecture over GF(2m). First we design a modular multiplier and a modular squarer, then propose an architecture by combing the multiplier and the squarer. All architectures use an irreducible AOP (All One Polynomial) as a modulus, which has the properties of all coefficients with '1'. The proposed architectures have lower hardware complexity than previous architectures. They could be. Therefore it is useful for implementing the exponentiation architecture, which is the con operation in public-key cryptosystems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.3 s.333
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• pp.35-42
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• 2005

This paper proposes a new reseeding methodology using a variable-rank multiple-polynomial linear feedback shift register (MP-LFSR). In the proposed reseeding scheme, a test cube with large number of specified bits is encoded with a high-rank polynomial, while a test cube with a small number of specified bits is encoded with a low-rank polynomial. Therefore, according to the number of specified bits in each test cube, the size of the encoded data can be optimally reduced. A variable-rank MP-LFSR can be implemented with a slight modification of a conventional MP-LFSR and Multiple Polynomial can be represented by adding just 1 bit to encoding data. The experimental results on the largest ISCAS'89 benchmark circuits show that the proposed methodology can provide much better encoding efficiency than the previous methods with adequate hardware overhead.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.333-340
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• 2018

This paper introduces a BCH code decoder using parallel CRC(: Cyclic Redundancy Check) generation. Using a conventional parallel syndrome generator with a LFSR(: Linear Feedback Shift Register), it takes up a lot of space for a short code. The proposed decoder uses the parallel CRC method that is widely used to compute the checksum. This scheme optimizes the a syndrome generator in the decoder by eliminating redundant xor operation compared with the parallel LFSR and thus minimizes chip area and propagation delay. In simulation results, the proposed decoder has accomplished propagation delay reduction of 2.01 ns as compared to the conventional scheme. The proposed decoder has been designed and synthesized in $0.35-{\mu}m$ CMOS process.