• International Journal of Advanced Culture Technology
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• v.11 no.1
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• pp.343-348
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• 2023

As the IoT market continues to grow, security threats to IoT devices with limited resources are also increasing. However, the application of security technology to the existing system to IoT devices with limited resources is impossible due to the inherent characteristics of IoT devices. Various methods for solving related problems have been studied in existing studies to solve this problem. Therefore, this study analyzes the characteristics of domestic IoT authentication standards and existing research to propose an algorithm that applies blockchain-based authentication and lightweight encryption algorithms to IoT equipment with limited resources. In this study, a key generation method was applied using a Lamport hash-chain and data integrity between IoT devices were provided using a Merkle Tree, and an LEA encryption algorithm was applied using confidentiality in data communication. In the experiment, it was verified that the efficiency is high when the LEA encryption algorithm, which is a lightweight encryption algorithm, is applied to IoT devices with limited resources.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.4
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• pp.888-894
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• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.401-403
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• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• Journal of Information Processing Systems
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• v.17 no.2
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• pp.253-270
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• 2021

In January 2013, the National Institute of Standards and Technology (NIST) announced the CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) contest to identify authenticated ciphers that are suitable for a wide range of applications. A total of 57 submissions made it into the first round of the competition out of which 6 were announced as winners in March 2019. In the process of the competition, NIST realized that most of the authenticated ciphers submitted were not suitable for resource-constrained devices used as end nodes in the Internet-of-Things (IoT) platform. For that matter, the NIST Lightweight Cryptography Standardization Process was set up to identify authenticated encryption and hashing algorithms for IoT devices. The call for submissions was initiated in 2018 and in April 2019, 56 submissions made it into the first round of the competition. In August 2019, 32 out of the 56 submissions were selected for the second round which is due to end in the year 2021. This work surveys the 32 authenticated encryption schemes that made it into the second round of the NIST lightweight cryptography standardization process. The paper presents an easy-to-understand comparative overview of the recommended parameters, primitives, mode of operation, features, security parameter, and hardware/software performance of the 32 candidate algorithms. The paper goes further by discussing the challenges of the Lightweight Cryptography Standardization Process and provides some suitable recommendations.

• Journal of Internet Computing and Services
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• v.18 no.5
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• pp.1-8
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• 2017

Lightweight Encryption Algorithm(LEA) was developed by National Security Research Institute(NSRI) in 2013 and targeted to be suitable for environments for big data processing, cloud service, and mobile. LEA specifies the 128-bit message block size and 128-, 192-, and 256-bit key sizes. In this paper, block cipher LEA algorithm which can encrypt and decrypt 128-bit messages is designed using Verilog-HDL. The designed IP for encryption and decryption has a maximum throughput of 874Mbps in 128-bit key mode and that of 749Mbps in 192 and 656Mbps in 256-bit key modes on Xilinx Vertex5. The cryptographic IP of this paper is applicable as security module of the mobile areas such as smart card, internet banking, e-commerce and IoT.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.10
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• pp.1460-1468
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• 2015

As the number of IoT service increases, the interest of lightweight block cipher algorithm, which consists of simple operations with low-power and high speed, is growing. LEA(Leightweight Encryption Algorithm) is recently adopted as one of lightweight encryption standards in Korea. In this paper a pipeline LEA architecture is proposed to process large amounts of data with high throughput. The proposed pipeline LEA can communicate with external modules in the 32-bit I/O interface. It consists of input, output and encryption pipeline stages which take 4 cycles using a muti-cycle pipeline technique. The experimental results showed that the proposed pipeline LEA achieved more than 7.5 Gbps even though the key length was varied. Compared with the previous high speed LEA in accordance with key length of 128, 192, and 256 bits, the throughput of the pipeline LEA was improved 6.45, 7.52, and 8.6 times. Also the throughput per area was improved 2, 1.82, and 2.1 times better than the previous one.

• Journal of the Korea Society of Computer and Information
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• v.23 no.10
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• pp.111-117
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• 2018

CHAM is a lightweight block cipher, proposed in ICISC 2017. CHAM-n/k has the n-bit block and the k-bit key, and designers recommend CHAM-64/128, CHAM-128/128, and CHAM-128/256. In this paper, we study how to make optimal software implementation of CHAM such that it has high encryption speed on CPUs with high computing power. The best performances of our CHAM implementations are 1.6 cycles/byte for CHAM-64/128, 2.3 cycles/byte for CHAM-128/128, and 3.8 cycles/byte for CHAM-128/256. The comparison with existing software implementation results for well-known block ciphers shows that our results are competitive.

• KIPS Transactions on Computer and Communication Systems
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• v.6 no.9
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• pp.397-406
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• 2017

In case of using the existing encrypted algorithm for massive data encryption service under the cloud environment, the problem that requires much time in data encryption come to the fore. To make up for this weakness, a partial encryption method is used generally. However, the existing partial encryption method has a disadvantage that the encrypted data can be inferred due to the remaining area that is not encrypted. This study proposes a partial encryption method of increasing the encryption speed and complying with the security standard in order to solve this demerit. The proposed method consists of 3 processes such as header formation, partial encryption and block shuffle. In step 1 Header formation process, header data necessary for the algorithm are generated. In step 2 Partial encryption process, a part of data is encrypted, using LEA (Lightweight Encryption Algorithm), and all data are transformed with XOR of data in the unencrypted part and the block generated in the encryption process. In step 3 Block shuffle process, the blocks are mixed, using the shuffle data stored with the random arrangement form in the header to carry out encryption by transforming the data into an unrecognizable form. As a result of the implementation of the proposed method, applying it to a mobile device, all the encrypted data were transformed into an unrecognizable form, so the data could not be inferred, and the data could not be restored without the encryption key. It was confirmed that the proposed method could make prompt treatment possible in encrypting mass data since the encryption speed is improved by approximately 273% or so compared to LEA which is Lightweight Encryption Algorithm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.584-586
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• 2017

In this paper we provide a unified crypto core that integrates lightweight symmetric cryptography and authentication. The crypto core implements a unified 128 bit key architecture of PRESENT encryption algorithm and a new lightweight encryption algorithm. The crypto core also consist of an authentication unit which neglects the use of hashing algorithms. Four algorithms are used for authentication which come from the Hopper-Blum (HB) and Hopper-Blum-Munilla-Penado (HB-MP) family of lightweight authentication algorithms: HB, HB+, HB-MP and HB-MP+. A unified architecture of these algorithms is implemented in this paper. The unified cryptosystem is designed using Verilog HDL, simulated with Modelsim SE and synthesized with Xilinx Design Suite 14.3. The crypto core synthesized to 1130 slices at 189Mhz frequency on Spartan6 FPGA device.

• Smart Media Journal
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• v.4 no.4
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• pp.39-46
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• 2015

This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.