• Journal of the Korean BIBLIA Society for library and Information Science
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• v.31 no.1
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• pp.193-212
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• 2020

In Korea, the term 'public library service population' is applied in various situations without academic discourse. This study analyzed concepts and applications of the term with literary reviews and case studies in United States, Australia, Japan, and Korea. And also this study redefined concepts and suggested new measurements of 'design population' and 'service population.' The former is the population who lives in area where public library can serve, and only demographic characteristics can be identified. It can be calculated based on the population of administrative district. In case of urban areas with a population of more than 100,000, it can be calculated the population within a radius of 2km from library. In areas with a population of less than 100,000 it can be calculated based on the population of Eup, Myeon, and Dong. In both cases the estimated population up to the library's opening year is added. Service population is used for the planning, evaluating, and promoting library services, and it can be defined as the actual users or estimated population determined by the input resources of the public libraries. It can be calculated by the number of enrolled members, or service participants, or target populations according to the size of input resources. The advantages of the proposal in this study are enabling efficient facility placement or resource inputs in public libraries and enhancing reliability of measuring output versus input. In addition, this study proposed to delete for paragraph 1 of Article 3 of the Library Act to avoid confusion.

• Journal of the Korean BIBLIA Society for library and Information Science
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• v.20 no.2
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• pp.183-196
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• 2009

The purpose of this study is to develop school library evaluation criteria by individual provincial office of education. Data was collected from several school library evaluation criteria. Based upon the data new evaluation criteria were developed in order to increase student academic achievement and apply various school environment. Evaluation items were divided into three items: library programs, school support, service. Evaluation methods were identified into survey method, statistics method, and applied standard statistics method. From three methods, applied standard statistics method was selected. This method included quantitative items and qualitative items. Quantitative items have two criteria from budget, three criteria from collection, and three criteria from use. Qualitative items have two criteria: collection and book usage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.