• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
• /
• pp.722-726
• /
• 2003

본 논문에서는 Porous poly-silicon cold cathode에 의해 전자를 방출하는 Ballistic electron surface-emitting display(BSD)의 전계방출 특성을 실험했다. BSD는 nanocrystalline을 둘러싼 산화막을 multi-tunneling한 전자에 의해 발광이 되는 mechanism이기 때문에 산화막의 두께를 변수로 두어 특성을 실험했다. 900℃에서 1시간에서 3시간까지 30분 간격으로산화 반응을 진행하였으며, leakage current와 emission current의 비로 효율을 나타내었을 때 1시간 30분 동안 산화 반응을 한 시료가 가장 좋은 특성을 나타내었다.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
• /
• pp.452-457
• /
• 1998

This paper deal with problems of leakage current, shaft voltage, bearing current, and EMI, in valiable-speed AC drives. The originating mechanism is illustrated with a high-frequency equivalent circuit. Reduction methods are classified in to six categories based on the equivalent circuit. Some experimental results show that a common-mode transformer (CMT) and a common-noise canceler (ACC) can solve the problems, which have been proposed the authors.

• 한국정보전자통신기술학회논문지
• /
• 제16권4호
• /
• pp.173-179
• /
• 2023

본 논문에서는 4세대 VNAND 공정으로 만들어진 Peri 소자의 스트레스 영역 별 time-dependent dielectric breakdown(TDDB) 열화 메커니즘을 분석하고, 기존의 수명 예측 모델보다 더 넓은 신뢰성 평가 영역에서 신속성과 정확성을 향상시킬 수 있는 수명 예측 보완 모델을 제시하였다. SiON 절연층 nMOSFET에서 5개의 Vstr 조건에 대해 각 10번의 constant voltage stress(CVS) 측정 후, stress-induced leakage current(SILC) 분석을 통해 저전계 영역에서의 전계 기반 열화 메커니즘과 고전계 영역에서의 전류 기반 열화 메커니즘이 주요함을 확인하였다. 이후 Weibull 분포로부터 time-to-failure(TF)를 추출하여 기존의 E-모델과 1/E-모델의 수명 예측 한계점을 확인하였고, 각 모델의 결합 분리 열화 상수(k)를 추출 및 결합하여 전계 및 전류 기반의 열화 메커니즘을 모두 포함하는 병렬식 상호보완 모델을 제시하였다. 최종적으로 실측한 TDDB 데이터의 수명을 예측할 시, 기존의 E-모델과 1/E-모델에 비해 넓은 전계 영역에서 각 메커니즘을 모두 반영하여 높은 스트레스에서 신속한 신뢰성 평가로 더 정확한 수명을 예측할 수 있음을 확인하였다.

• KSTLE International Journal
• /
• 제3권2호
• /
• pp.79-83
• /
• 2002

Sealing an oil-air mixture plays important roles to have an enhanced lubrication for high speed spindle. High speed spindle requires non-contact type of sealing mechanism. Current work emphases on the investigation of the air jet effect on the protective collar type labyrinth seal. To improve the sealing capability of conventional labyrinth seal, air jet was injected against through the leakage flow, It has a combined geometry of a protective collar type and an air jet type. Both of a numerical analysis by CFD (Computational Fluid Dynamics) and experimental measurements are carried out to verify sealing improvement The sealing effects of the leakage clearance and the air jet magnitude are studied in various parameters. The results of pressure drop in the experiment match reasonably to those of the simulation by introducing a flow coefficient Effect of sealing improvement is explained as decreasing of leakage clearance by air jetting. Thus, sealing effect is improved by amount of air jetting even though clearance becomes larger.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제3권3호
• /
• pp.145-152
• /
• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• 전자공학회논문지A
• /
• 제31A권12호
• /
• pp.64-70
• /
• 1994

In this paper, we inverstigated how a parricular internal inverter circuit, which is located far from the input protection in CMOS DRAM, can be easily damaged by external ESD stress, while the protection circuit remains intact. It is shown in a mega bit DRAM that the internal circuit can be safe from ESD by simply improving the input protection circuit. An inverter, which consists of a relatively small NMOSFET and a very large PMOSFET, is used to speed up DRAMs, and the small NMOSFET is vulnerable to ESD in case that the discharge current beyond the protection flows through the inverter to Vss or Vcc power lines on chip. This internal circuit damage can not be detected by only measuring input leakage currents, but by comparing the standby and on operating current before and after ESD stressing. It was esperimentally proven that the placement of parasitic bipolar transistor between input pad and power supply is very effective for ESD immunity.

• 대한전자공학회논문지SD
• /
• 제39권10호
• /
• pp.25-34
• /
• 2002

본 논문에서는 코발트 실리사이드가 형성된 얕은 p+-n과 n+-p 접합의 전류-전압 특성을 분석하여 silicidation에 의해 형성된 Schottky contact 면적을 구하였다. 역방향 바이어스 영역에서는 Poole-Frenkel barrier lowering 효과가 지배적으로 나타나서 Schottky contact 효과를 파악하기가 어려웠다. 그러나 Schottky contact의 형성은 순방향 바이어스 영역에서 n+-p 접합의 전류-전압 (I-V) 동작에 영향을 미치는 것으로 확인되었다. 실리사이드가 형성된 n+-p 다이오드의 누설전류 증가는 실리사이드가 형성될 때 p-substrate또는 depletion area로 코발트가 침투퇴어 Schottky contact을 형성하거나 trap들을 발생시켰기 때문이다. 분석결과 perimeter intensive diode인 경우에는 silicide가 junction area까지 침투하였으며, area intensive junction인 경우에는 silicide가 비록 공핍층이나 p-substrate까지 침투하지는 않았더라도 공핍층 근처까지 침투하여 trap들을 발생시켜 누설전류를 증가시킴을 확인하였다. 반면 p+-n 다이오드의 경우 Schottky contact이발생하지 않았고 따라서 누설전류도 증가하지 않았다. n+-p 다이오드에서 실리사이드에 의해 형성된 Schottky contact 면적은 순방향 바이어스와 역방향 바이어스의 전류 전압특성을 동시에 제시하여 유도할 수 있었고 전체 접합면적의 0.01%보다 작게 분석되었다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제54권11호
• /
• pp.483-489
• /
• 2005

This study performs a simulation for an accumulation mechanism of contaminants, which were produced in an industrial belt of inland, on the surface of insulators. From the simulation, silicon insulators presented higher accumulation than that of EPDM(Ethylene Propylene Diene Terpolymer : EPDM) insulators on the same distance in the case of the Virgin polymer insulator, and this result presented the same result in the insulator applied in actual fields. In the case of the accumulation test for the Virgin insulator and insulators used in actual fields, it is evident that the Virgin insulator presented more accumulation than that of the insulator used in actual fields. The results can be caused by the generation of LMW (Low Molecular Weight) on the external material of polymer insulators, and the level of the accumulation can be changed according to the degree of the continuous generation of LMW. In order to simulate a certain pollution of an industrial belt, which is located along the coastline, leakage currents were measured by applying the contaminant compulsively that was produced with salts and Kaolin according to the ratio of its weight on the surface of insulators. The more increase in the content of Kaolin pollution, the level of leakage currents on the surface of polymer insulator more increased. In addition, the approaching time to the maximum value of leakage currents presented a nearly constant level regardless of the content of Kaolin. The level of leakage currents significantly decreased according to the passage of time, and the level of leakage currents on the surface maintained a constant level at a specific time regardless of the content of Kaolin.

• 대한전기학회논문지
• /
• 제36권4호
• /
• pp.259-266
• /
• 1987

In order to drive motor control system precisely, the motor is to be controlled by mmfs and current with sinusoidal waveforms. In this paper the Delta Modulation (DM) Technique is used for generating PWM pulse with sinusoidal waveform. However the motor currents yet contain odd harmonics due to leakage inductances, speed and exitation. To reduce harmonics, the parameter adaptive control method is introduced. That is, Req.C parameter of Delta Modulator is controlled adaptively by parameter adaptor. The adaptive signal is achieved by the difference between motor current and reference waveform, and this signal is converted to the voltage commend signal by adaptive mechanism. The test reslts show that this system is operated smoothly over a wide range of motor speed and motor current is controlled to be sinusoidal waveform adaptively.

• 한국산업정보학회논문지
• /
• 제18권1호
• /
• pp.19-24
• /
• 2013

As CMOS technology is scaled down more aggressively, the reliability mechanism (or aging effect) caused by the diffusion of metal atoms along the conductor in the direction of the electron flow, also called electromigration (EM), has become a major reliability concern. With the present of EM, it is difficult to control the current flows of the MOSFET device and interconnect. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the EM effects on current of the nanoscale CMOS circuits are analyzed. Finally, this paper introduces an on-chip current measurement method providing lifetime electromigration management which are designed using 45-nm CMOS predictive technology model.