• Title/Summary/Keyword: Latch

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Process Design of Trimming to Improve the Sheared-Edge of the Vehicle Door Latch based on the FE Simulation and the Taguchi Method (유한요소해석 및 다구찌법을 이용한 자동차 도어 래치의 전단면 품질 향상을 위한 트리밍 공정 설계)

  • Lee, Jung-Hyun;Lee, Kyung-Hun;Lee, Seon-Bong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.17 no.11
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    • pp.483-490
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    • 2016
  • Automobile door latch is a fine design and assembly techniques are required in order to produce them in a small component assembly shape such as a spring, injection products, a small-sized motor. The door latch is fixed to not open the door of the car plays an important role it has a direct impact on the driver's safety. In this study, during trimming of the terminals of the connector main components of the car door latch, reduce rollover and conducted a research to find a suitable effective shear surface. Using the Taguchi method with orthogonal array of Finite Element Analysis and optimal Design of Experiments were set up parameters for the shear surface quality of the car door latch connector terminals. The design parameters used in the analysis is the clearance, the radius, and the blank holding force, the material of the connector terminal is a C2600. Trimming process optimum conditions suggested by the analysis has been verified by experiments, the shear surface shape and dimensions of a final product in good agreement with forming analysis results.Taguchi method from the above results in the optimization for the final rollover and effective shear surface improved for a vehicle door latch to the connector terminal can be seen that the applicable and useful for a variety of metal forming processes other than the trimming process is determined to be applicable.

Simulation of a Novel Lateral Trench Electrode IGBT with Improved Latch-up and Forward Blocking Characteristics

  • Kang, Ey-Goo;Moon, Seung-Hyun;Kim, Sangsig;Sung, Man-Young
    • Transactions on Electrical and Electronic Materials
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    • v.2 no.1
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    • pp.32-38
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    • 2001
  • A new small sized Lateral Trench electrode Insulated Gate Bipolar Transistor(LTEIGBT) was proposed to improve the characteristics of conventional Lateral IGBT (LIGBT) and Lateral Trench gate IGBT (LTIGBT). The entire electrode of LTEIGBT was replace with trench-type electrode. The LTEIGBT was designed so that the width of device was no more than 19 ㎛. The Latch-up current densities of LIGBT, LTIGBT and the proposed LTEIGBT were 120A/㎠, 540A/㎠, and 1230A/㎠, respectively. The enhanced latch-up capability of the LTEIGBT was obtained through holes in the current directly reaching the cathode via the p+ cathode layer underneath n+ cathode layer. The forward blocking voltage of the LTEIGBT is 130V. Conventional LIGBT and LTIGBT of the same size were no more than 60V and 100V, respectively. Because the the proposed device was constructed of trench-type electrodes, the electric field moved toward trench-oxide layer, and punch through breakdown of LTEIGBT is occurred, lately.

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Study on Fabrication of The Lateral Trench Electrode IGBT with a p+ Diverter having Excellent Electrical Characteristics (우수한 전기적 특성을 갖는 p+ 다이버터를 갖는 LTEIGBT의 제작에 관한 연구)

  • 김대원;박전웅;김대종;오대석;강이구;성만영
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.342-345
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    • 2002
  • A new lateral trench electrode IGBT with p+ diverter was Proposed to suppress latch-up of LTIGBT. The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEIGBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occurred at an anode current density of 540A/$\textrm{cm}^2$. And the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. That of the conventional LTIGBT of the same size was no more than 105V. When the gate voltage is applied 12V, the forward conduction currents of the Proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90mA and 70mA, respectively, at the same breakdown voltage of 150V.

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A Latch-Up Immunized Lateral Trench IGBT with $p^{+}$ Diverter Structure for Smart Power IC (스마트 파워 IC를 위한 $p^{+}$ Diverter 구조의 횡형 트랜치 IGBT)

  • 문승현;강이구;성만영;김상식
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.14 no.7
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    • pp.546-550
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    • 2001
  • A new Lateral Trench Insulated Gate Bipolar Transistor(LTIGBT) with p$^{+}$ diverter was proposed to improve the characteristics of the conventional LTIGBT. The forward blocking voltage of the proposed LTIGBT with p$^{+}$ diverter was about 140V. That of the conventional LTIGBT of the same size was 105V. Because the p$^{+}$ diverter region of the proposed device was enclosed trench oxide layer, he electric field moved toward trench-oxide layer, and punch through breakdown of LTIGBT with p$^{+}$ diverter was occurred, lately. Therefore, the p$^{+}$ diverter of the proposed LTIGBT didn't relate to breakdown voltage in a different way the conventional LTIGBT. The Latch-up current densities of the conventional LTIGBT and proposed LTIGBT were 540A/$\textrm{cm}^2$, and 1453A/$\textrm{cm}^2$, respectively. The enhanced latch-up capability of the proposed LTIGBT was obtained through holes in the current directly reaching the cathode via the p$^{+}$ divert region and p$^{+}$ cathode layer beneath n$^{+}$ cathode layer./ cathode layer.

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Study on Electrical Characteristics of the Fabricated Lateral Trench Electrode IGBT with p+ Diverter (효율적인 p+ 다이버터를 갖는 수평형 트렌치 전극형 IGBT의 제작에 따른 전기적 특성에 관한 연구)

  • 강이구;김상식;성만영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.9
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    • pp.750-757
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    • 2002
  • A new lateral trench LTEIGBT with p+ diverter was proposed to suppress latch-up of LTIGBT The p+ diverter was placed between the anode and cathode electrode. The latch-up of LTEICBT with a p+ diverter was effectively suppressed to sustain an anode voltage of 8.7V and a current density of 1453A/$\textrm{cm}^2$ while in the conventional LTIGBT, latch-up occured at an anode current density of 540A/$\textrm{cm}^2$. In addition, the forward blocking voltage of the proposed LTEIGBT with a p+ diverter was about 140V. The forward blocking voltage of the conventional LTIGBT of the same size was no more than 105V, We fabricated the proposed LTEIGBT with a p+ diverter after the device and process simulation was finished. When the gate voltage is applied 12V, the forward conduction currents of the proposed LTEIGBT with a p+ diverter and the conventional LIGBT are 90㎃ and 70㎃, respectively, at the same breakdown voltage of 150V.

Study on New LIGBT with Multi Gate for High Speed and Improving Latch up Effect (래치 업 특성의 개선과 고속 스위칭 특성을 위한 다중 게이트 구조의 새로운 LIGBT)

  • 강이구;성만영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.5
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    • pp.371-375
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    • 2000
  • In this paper a new conductivity modulated power transistor called the Lateral Insulated Gated Bipolar Transistor which included n+ ring and p-channel gate is presented. A new lateral IGBT structure is proposed to suppress latch-up and to improve turn off time by imploying n+ ring and p-channel gate and verified by MEDICI. The simulated I-V characteristics at $V_{G}$=15V show that the latch up occurs at $V_{A}$=18V and 6.9$\times$10$^{-5}$ A/${\mu}{\textrm}{m}$ for the proposed LIGBT while the conventional LIGBT latches at $V_{A}$=1.3V and 1.96${\mu}{\textrm}{m}$10$^{-5A}$${\mu}{\textrm}{m}$. It is shown that turn off characteristic of new LIGBT is 8 times than that of conventional LIGBT. And noble LIGBT is not n+ buffer layer because that It includes p channel gate and n+ ring. Therefore Mask for the buffer layer isn’t needed. The concentration of n+ ring is and the numbers of n+ ring and p channel gate are three for the optimal design.n.n.n.n.

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Two Version Latch Technique for Metadata Management of Documents in Digital Library (전자 도서관에서 문서의 메타데이타 관리를 위한 2 버전 래치 기법)

  • Jwa, Eun-Hee;Park, Seog
    • Journal of KIISE:Databases
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    • v.29 no.3
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    • pp.159-167
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    • 2002
  • Recently, a major issue in the research of metadata is the standardization of metadata format. The new extension capability of metadata in the standardization requires some changes - storing and managing dynamic data consistently. In this paper, we define the characteristics of new metadata and propose a concurrency control called Two Version Latch (2VL). 2VL uses a latch and maintains two versions. Maintaining two versions using latch minimizes conflicts between read operation and write operation. The removal of unnecessary lock holding minimizes refresh latency. Therefore, this algorithm presents fast response time and recent data retrieval in read operation execution. As a result of the performance evaluation, the 2VL algorithm is shown to be better than other algorithms in metadata management system.

Optimum Latch Contour Design for Improving Gas Circuit Breaker Performance (가스회로차단기의 성능 개선을 위한 윤곽 최적설계)

  • Choi, Gyu Seok;Cha, Hyun Kyung;Sohn, Jeong Hyun;Yoo, Wan Suk
    • Transactions of the Korean Society of Mechanical Engineers A
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    • v.38 no.1
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    • pp.25-30
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    • 2014
  • The dynamic characteristics of a gas circuit breaker depend on the underlying high-speed operating mechanism with a spring-actuated latch system. Many studies have been carried out to reduce the breaking time of circuit breakers. In this study, the optimum latch contour design is determined for reducing the breaking time of a circuit breaker. A multi-body dynamic model of the latch is established for analyzing the dynamic behaviors of the circuit breaker by using the MSC/ADAMS program. Simulation results are matched against experimental data. VisualDoc is employed for determining the optimal latch contour. From the optimum design, the breaking time of a gas circuit breaker is improved by about 8.6%.

Low Power Test for SoC(System-On-Chip)

  • Jung, Jun-Mo
    • Journal of information and communication convergence engineering
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    • v.9 no.6
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    • pp.729-732
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    • 2011
  • Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

Study of Bit Line Sense Amplifier for MRAM (MRAM의 Bit Line Sense Amplifier에 대한 연구)

  • 홍승균;김인모;유혜승;김수원;송상훈
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.40 no.10
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    • pp.63-67
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    • 2003
  • This paper proposes a new BLSA(Bit Line Sense Amplifier) for MRAM. Current BLSA employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed BLSA simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speedas the latch-type BLSA in simulation and occupies only 85% of the area taken by the latch-type BLSA.