• 한국공작기계학회논문집
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• 제15권3호
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• pp.82-90
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• 2006

Recently the electrostatic 2-axis MEMS stages have been fabricated for the purpose of an application to PSD (Probe-based Storage Device). However, all of the components(platform, comb electrodes, springs, anchors, etc.) in those stages are placed in-plane so that they have low areal efficienceis, which is undesirable as data storage devices. In this paper, we present a novel structure of an electrostatic 2-axis MEMS stage that is characterized by having large area platform. for obtaining large area efficiency, the actuator part consisting of mainly comb electrodes and springs is placed right below the platform. The structure and operational principle of the MEMS stage are described, followed by a design procedure, structural and modal analyses using FEM(Finite Element Method). The areal efficiency of the MEMS stage was designed to be about 25%, which is very large compared with the conventional ones having a few percentage.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2004년도 추계학술대회 논문집
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• pp.373-378
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• 2004

Recently the electrostatic 2-axis MEMS stages have been fabricated for the purpose of an application to PSD (Probebased Storage Device). However, most of them have low area efficiency, which is undesirable as data storage devices, since all of the components (springs, comb electrodes, anchors, platform, etc.) are placed in-plane. In this paper, we present a novel structure of electrostatic 2-axis MEMS stage that is characterized by having large area platform. For large area efficiency, the actuator part consisting of mainly comb electrodes and springs is placed right below the platform. In this article, the structures and operational principle of the MEMS stages are described, followed by design procedure, structural and modal analysis using FEM(Finite Element Method). The area efficiency of the MEMS stage was designed to be about 55％, that is very large compared with conventional ones having a few percentage.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2005년도 춘계 학술발표회 논문집
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• pp.974-981
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• 2005

Because general laboratory tests for sand compaction pile method including unit-cell test device have fixed outside diameter, as area replacement ratio increase, diameter of sand pile increase. These condition can bring about overestimation of stiffness of composite ground. In addition, existing large soil box which consist of bellows type loading plate can occur serious mistake in checking the amount of drained water because there are additional drainage along the inside wall in device. Overcoming these shortcoming, this paper developed modified large scale soil box consist of piston type load plate. In this study, using this device, series of modified large scale soil box tests were performed, and investigated the settlement and stress transportation characteristics with area replacement ratio in sand compaction pile method.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.923-926
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• 2009

We fabricated large-area OLED lighting device using screen printing. In order to operate full area of large-area OLED uniformly, each cell in OLED panel was designed to work separately. We connected OLED panel with a PCB electrically using jig pins so that each cell could be operated individually. In this presentation, we report a few important issues on the fabrication of large-area OLED for lighting applications.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2009년도 추계학술발표대회
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• pp.5.1-5.1
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• 2009

Organic photovoltaic (OPV)cells have attracted considerable attention due to their potential for flexible, lightweight, and low-cost application of solar energy conversion. Since a 1% power conversion efficiency (PCE) OPV based on a single donor-acceptor heterojunction was reported by Tang, the PCE has steadily improved around 5%. It is well known that a high parallel (shunt)resistance and a low series resistance are required simultaneously to achieve ideal photovoltaic devices. The device should be free of leakage current through the device to maximize the parallel resistance. The series resistance is attributed to the ohmic loss in the whole device, which includes the bulk resistance and the contact resistance. The bulk resistance originated from the bulk resistance of the organic layer and the electrodes; the contact resistance comes from the interface between the electrodes and the active layer. Furthermore, it has been reported that the bulk resistance of the indium tin oxide (ITO) of the devices dominates the series resistance of OPVs for a large area more than $0.01\;cm^2$. Therefore, in practical application, the large area of ITO may significantly reduce the device performance. In this work, we investigated the effect of sheet resistance ($R_{sh}$) of deposited ITO on the performance of OPVs. It was found that the device performance of polythiophene-fullerene (P3HT:PCBM) bulk heterojunction OPVs was critically dependent on Rsh of the ITO electrode. With decreasing $R_{sh}$ of the ITO from 39 to $8.5\;{\Omega}/{\square}$, the fill factor (FF) of OPVs was dramatically improved from 0.407 to 0.580, resulting in improvement of PCE from $1.63{\pm}0.2$ to $2.5{\pm}0.1%$ underan AM1.5 simulated solar intensity of $100\;mW/cm^2$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.658-658
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• 2013

Graphene is an attractive material for various device applications due to great electrical properties and chemical properties. However, lack of band gap is significant hurdle of graphene for future electrical device applications. In the past few years, several methods have been attempted to open and tune a band gap of graphene. For example, researchers try to fabricate graphene nanoribbon (GNR) using various templates or unzip the carbon nanotubes itself. However, these methods generate small driving currents or transconductances because of the large amount of scattering source at edge of GNRs. At 2009, Bai et al. introduced graphene nanomesh (GNM) structures which can open the band gap of large area graphene at room temperature with high current. However, this method is complex and only small area is possible. For practical applications, it needs more simple and large scale process. Herein, we introduce a photosensitive graphene device fabrication using CdSe QD coated nano-porous graphene (NPG). In our experiment, NPG was fabricated by thin film anodic aluminum oxide (AAO) film as an etching mask. First of all, we transfer the AAO on the graphene. And then, we etch the graphene using O2 reactive ion etching (RIE). Finally, we fabricate graphene device thorough photolithography process. We can control the length of NPG neckwidth from AAO pore widening time and RIE etching time. And we can increase size of NPG as large as 2 $cm^2$. Thin CdSe QD layer was deposited by spin coatingprocess. We carried out NPG structure by using field emission scanning electron microscopy (FE-SEM). And device measurements were done by Keithley 4200 SCS with 532 nm laser beam (5 mW) irradiation.

• 한국정밀공학회지
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• 제23권9호
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• pp.179-189
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• 2006

Recently the electrostatic 2-axis MEMS stages have been fabricated f3r the purpose of an application to PSD (Probe-based Storage Device). However, all of the components (platform, comb electrodes, springs, anchors, etc.) in those stages are placed in-plane so that they have low areal efficiencies such as a few percentage, which is undesirable as data storage devices. In this paper, we present a novel structure of an electrostatic 2-axis MEMS stage that is characterized by having a large areal efficiency of about 25%. For obtaining large area efficiency, the actuator part consisting of mainly comb electrodes and springs is placed right below the platform. The structure and operational principle of the MEMS stage are described, followed by a design and analysis, the fabrication and measurement results. Experimental results show that the driving ranges of the fabricated stage along the x and y axis were 27$\mu$m, 38$\mu$m at the supplied voltages of 65V, 70V, respectively and the natural frequencies along x and y axis were 180Hz, 310Hz, respectively. The total size of the stage is about 5.9$\times$6.8mm$^2$ and the platform size is about 2.7$\times$3.6mm$^2$.

• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.53-59
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• 2011

Recently there have been considerable attentions on nanoimprint lithography (NIL) by the display device and semiconductor industry due to its potential abilities that enable cost-effective and high-throughput nanofabrication. Although one of the current major research trends of NIL is large-area patterning, the technical difficulties to keep the uniformity of the residual layer become severer as the imprinting area increases more and more. In this paper we focused on the deformation of the $2^{nd}$ generation TFT-LCD sized ($370{\times}470mm^2$) large-area soft mold in the UV imprinting process. A mold was fabricated with PDMS(Poly-dimethyl Siloxane) layered glass back plate(t0.5). Besides, the mold includes large surrounding wall type protrusions of 1.9 mm width and the via-hole(7 ${\mu}m$ diameter) patterend area. The large surrounding wall type protrusions cause the proximity effect which severely degrades the uniformity of residual layer in the via-hole patterend area. Therefore the deformation of the mold was calculated by finite element analysis to assess the effect of large surrounding wall type protrusions and the flexiblity of the mold. The deformation of soft mold was verified by the measurements qualitatively.

• 반도체디스플레이기술학회지
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• 제21권3호
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• pp.125-129
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• 2022

The current display technology tends to be highly integrated with high resolution, the element size is gradually downsized, and the structure becomes complicated. Inductively coupled plasma (ICP) dry etcher of various types of etching equipment is a structure that places a large multi-divisional antenna source on the top lid, passes current to the Antenna, and generates plasma using the induced magnetic field generated at this time. However, in the case of a device of a large area size, a support that can withstand a load structurally is necessary, and when these support portions are applied, arrangement of antenna becomes difficult, which causes reduction in uniformity. As described above, the development of antenna source of a large area having a uniform plasma density on the whole surface is difficult to restrict hardware (H/W). As a solution to this problem, we confirmed the change in uniformity of plasma by applying two kinds of specific shape faraday shield(FICP) to the lower part of the large area upper lid antenna of 6 and 8th more than that generation size. In this thesis, we verify the faraday shield effect which can improve plasma uniformity control of ICP dry etcher equipment applied to medium and large displays.

• 한국정보처리학회논문지
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• 제6권5호
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• pp.1351-1361
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• 1999

The wide spread of multimedia system demands a large area viewing display device which can inform a message to many people in open area. This paper is about the design of a large area viewing LED panel control system. The control system runs on 16 bit microprocessor MC68EC000 and has following functions: 16 line clock and time, 2 channel priority interrupt, 2 channel direct memory access, 2 channel 12 bit clock and timer, 2 channel infrared remocon receiver, 2 channel RS-232C with 16 byte FIFO, IBM PC/AT compatible keyboard interface, ISA bus, battery backuped real time clock, battery backuped 256 byte SRAM and watch dog timer. The core circuits are implemented to ASIC, considering lower cost, higher reliability, higher performance, smaller dimension, and lower power consumption. This is verified by simulation and fabricated in 0.6 um CMOS SOG processes. The total gate count is 39,083 and the clock frequency is 48 MGz. The fabricated ASIC is mounted on test board.