• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권1호
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• pp.95-97
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• 2007

Large area flicker is one of the most annoying image defects, and it is an inherent characteristic of impulsively driven displays such as CRTs. Recently, LCDs have also adopted impulsive driving methods for improved motion picture quality, therefore LCDs can also show large area flicker. Existing metrics do not account for the non-linearity of human brightness perception. This paper presents an improved large area flicker metric to more accurately quantify large area display flicker performance.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 1995년도 학술대회
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• pp.87-90
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• 1995

In this paper, we propose a new deinterlacing algorithm based on weighted wide vector correlations. This algorithm is developed mainly for the format conversion problem encountered in current HDTV system, but not limited to. By having wide vector correlations, visually annoying artifacts caused by interlacing, such as a serrate line, line crawling, a line flicker, and a large area flicker, can be remarkably reduced, since the use of wide vector correlation increases the detectability of edges in various orientations.

• 방송공학회논문지
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• 제1권1호
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• pp.44-54
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• 1996

In this paper, we propose a new 3-D deinterlacing algorithm based on wide sparse vector correlations and a vertical edge based motion detection algorithm. which is an extension of the deinterlacing algorithm proposed in [10. llJ by the authors. The prooised algorithm is developed mainly for the format conversion problem encountered in current HDTV system, but can also be aplicable to the double scan conversion problesm frequently encountered in ths NTSC systems. By exploiting the edge oriented spatial interpolation based on the wide vector correlations, visually annoying artifiacts caused by interlacing such as a serrate line. line crawling, a line flicker, and a large area flicker can be remarkably reduced since the use of the wide vectors increases the range of the edge orientations that can be detected, and by exploiting sparse vectors correlations the HjW complexity for realizing the algorithm in applications cam be significantly simplified. Simulations are provided indicating thet the proposed algorithm results in a high performance comparable to the performance of the deinterlacing algorithm. based on the wide vector correlations.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.278-285
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• 2012

A digital readout IC for capacitive sensors is presented. Digital capacitance readout circuits suffer from static capacitance of sensors, especially single-ended sensors, and require large passive elements to cancel such DC offset signal. For this reason, to maximize a dynamic range with a small die area, the proposed circuit features digital filters having a coarse and fine compensation steps. Moreover, by employing switched-capacitor circuit for the front-end, correlated double sampling (CDS) technique can be adopted to minimize low-frequency device noise. The proposed circuit targeted 8-kHz signal bandwidth and oversampling ratio (OSR) of 64, thus a $3^{rd}$-order ${\Delta}{\Sigma}$ modulator operating at 1 MH was used for pulse-density-modulated (PDM) output. The proposed IC was designed in a 0.18-${\mu}m$ CMOS mixed-mode process, and occupied $0.86{\times}1.33mm^2$. The measurement results shows suppressed DC power under about -30 dBFS with minimized device flicker noise.