• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.22-34
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• 2010

Existing image scalers generally adopt simple interpolation methods such as bilinear method to take cost-benefit, or highly complex architectures to achieve high quality resulting images. However, demands for a low power, low cost, and high performance image scaler become more important because of emerging high quality mobile contents. In this paper we propose the novel low power hardware architecture for a high quality raster scan image scaler. The proposed scaler architecture enhances the existing cubic interpolation look-up table architecture by reducing and optimizing memory access and hardware components. The input data buffer of existing image scaler is replaced with line memories to reduce the number of memory access that is critical to power consumption. The cubic interpolation formula used in existing look-up table architecture is also rearranged to reduce the number of the multipliers and look-up table size. Finally we analyze the optimized parameter sets of look-up table, which is a trade-off between quality of result image and hardware size.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.131-144
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• 2015

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5B
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• pp.429-436
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• 2011

The G-PON is an efficient solution to implement the FTTH and have GEM frame to accomodate various protocols like Ethernet frames, IP packets, and TDM signals. Above all, the Ethernet is one of the most widely used 2nd layer protocol in the campus, the subscriber access, and the carrier service. So G-PON system has to provide an Ethernet interface with top priority. In this paper, we implement a gigabit Ethernet adapter based on Ethernet over GEM in the ITU-T G.984.3 to accommodate Ethernet protocol in the G-PON TC chip. The adapter maps each Ethernet frame to a single or multiple GEM frames and has several functions including generation of the GEM header, encapsulation of frames and the SAR. In particular, the adapter have converter (LUT) MAC address to port-ID which is a key to identify logical connections though it is not defined in specification but important. We implement the adapter with a FPGA and verify the functions of segmentation and reassembling, MAC address learning, and throughput with the logic analyzer and the Ethernet analyzer.

• Journal of IKEEE
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• v.15 no.2
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• pp.113-121
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• 2011

This paper presents the design of a fast auxiliary channel bus for DisplayPort 1.2 interface. The fast auxiliary channel supports Manchester transactions at 1Mbps and fast auxiliary transactions at 780Mbps. The Manchester transaction is used for managing the main link and auxiliary channel and the fast auxiliary transaction is for data transfer via the auxiliary channel. Simplified serial bus architecture is proposed to be implemented in fast auxiliary channel. The fast auxiliary channel transmitter and receiver are implemented with 7,648 LUTs and 6,020 slice register synthesized in Xilinx Vertex4 FPGA and can be operated at 72MHz to support 720Mbps.

• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.137-138
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• 2008

This paper proposes the modified image contrast enhancement technique for small-sized display of mobile handset. Sample images are user interface images, in which scaled up wVGA($800{\times}480$) from qVGA($320{\times}240$) that we can see easily in mobile handset. The display size of mobile handset is relatively small, so the goal of this paper is to simplify image contrast enhancement algorithm based on conventional HE (Histogram Equalization) algorithm and improve computational effectiveness to minimize power consumption in real hardware IC. In this paper, we adopt HE technique, which is classical and widely used for image contrast enhancement. At first, the input frame image is partitioned to temporal sub-frames and then analyzes gray level histogram of each sub-frame. In case that the analyzed histogram of some sub-frames deviates so much from reference level (it means that the sub-frame image components consist of too bright ones or dark ones), apply DHE(Dynamic Histogram Equalization) algorithm. In the other case, apply classical Histogram Linearization (or Global HE) algorithm. Also we compare the HE technique with gamma LUT (Look-Up Table) method, which is known as the simplest technique to enhance image contrast.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.146-150
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• 2015

The COSPAS-SARSAT committee decides MEOSAR (Medium-Earth Orbit for search and rescue) service development for installing 406MHz SAR instruments on their respective MEO navigation satellite system of the United States, EU, and Russia, since 2000. The transmitted beacon signal is separately arrived by satellites with different FOA (Frequency of Arrival) and TOA (Time of Arrival). It is directly transferred to MEOLUT. In MEOLUT, a LUT track at least 3 or 4 satellites simultaneously and estimate location of beacon using time difference of arrival (TDOA) and frequency difference arrival (FDOA). But the transmitted distress signals may be overlapped each other because the distress beacons transmit signal on mean interval of 50 seconds in arbitrary time. It's difficult that simultaneously estimate location of beacon by current scheme for several overlapped distress signal. So we use cross ambiguity function (CAF) Map algorithm and present Multi-CAF MAP scheme in order to satisfy performance requirement of system. The performance is analyzed for COSAPS-SARSAT MEOSAR.

• Journal of Korea Multimedia Society
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• v.15 no.10
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• pp.1247-1256
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• 2012

There are many filter based image processing algorithms and they usually require a huge amount of computations and memory accesses making it hard to attain a real-time performance, expecially in embedded applications. In this paper, we propose a pipelined hardware structure of the filter based face detection algorithm to show that the real time performance can be achieved by hardware design. In our design, the whole computation is divided into three pipeline stages: resizing the image (Resize), Transforming the image (ICT), and finding candidate area (Find Candidate). Each stage is optimized by considering the parallelism of the computation to reduce the number of cycles and utilizing the line memory to minimize the memory accesses. The resulting hardware uses 507 KB internal SRAM and occupies 9,039 LUTs when synthesized and configured on Xilinx Virtex5LX330 FPGA. It can operate at maximum 165MHz clock, giving the performance of 108 frame/sec, while detecting up to 20 faces.

• Journal of Korea Multimedia Society
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• v.9 no.4
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• pp.451-459
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• 2006

Color reproduction of small LCD display is quite different from that of standard CRT due to the difference of physical, electrical, and optical characteristics. In this paper, we propose a simple and practical method using gamma and CCT correction for improvement of color reproduction on a small LCD display. First, we investigate characteristics of a small LCD display such as brightness, uniformity, color temperature, white and black balance, and nonlinear gamma. And, we also analyze color reproduction region and CCT trajectory according to LCD's input levels. Finally, the optimum gamma and CCT compensation method using LUT is proposed, and our proposed method was realized at mobile phone without hardware modification. In the experimental results, the result image of proposed algorithm is more close to standard color.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.92-100
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• 2009

In this paper, we analyze the hardware architecture of Low Density Parity Check (LDPC) decoder using Log Likelihood Ration-Belief Propagation (LLR-BP) decoding algorithm. Various design issues that affect the decoding performance and the hardware complexity are discussed and the tradeoffs between the hardware complexity and the performance are analyzed. The message data for passing error probability is quantized to 7 bits and among them the fractional part is 4 bits. To maintain the decoding performance, the integer and fractional parts for the intrinsic information is 2 bits and 4 bits respectively. We discuss the alternate implementation of $\Psi$(x) function using piecewise linear approximation. Also, we improve the hardware complexity and the decoding time by applying overlapped scheduling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.64-71
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• 2009

This paper presents an efficient frame synchronizer architecture using the common autocorrelator for Digital Video Broadcasting via Satellite, Second generation(DVB-S2). To achieve the satisfactory performance under severe channel conditions and the efficient hardware resource utilization of functional synchronization blocks which have been implemented, we propose a new efficient common autocorrelator structure. The proposed architecture can improve the performance of the frame and frequency synchronizer since each block operates jointly in parallel and significantly reduce the complexity of the frame synchronizer. Hence, The proposed architecture can ensure the decrease by about 92% multipliers and 81% adders compared with the direct implementation. Moreover, it has been thoroughly verified with an FPGA board and R&STM SFU broadcast test equipment and consists of 29,821 LUTs with XilinxTM Virtex IV LX200.