• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.360-363
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• 1999

Video data compression is a major key technology in the field of multimedia applications. Variable-length coding is the most popular data compression technique which has been used in many data compression standards, such as JPEG, MPEG and image data compression standards, etc. In this paper, we present memory efficient VLC decoder architecture for MPEG-2 application which can achieve small memory space and higher throughput. To reduce the memory size, we propose a new grouping, remainder generation method and merged lookup table (LUT) for variable length decoders (VLD's). In the MPEG-2, the discrete cosine transform (DCT) coefficient table zero and one are mapped onto one memory whose space requirement has been minimized by using efficient memory mapping strategy The proposed memory size is only 256 words in spite of mapping two DCT coefficient tables.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.1
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• pp.26-30
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• 2012

In this paper, we propose a signal generation method of rectangular QAM for rotationally invariant I/Q TCM. The proposed method consists of only digital logic gates without look-up table so that we can implement the system compactly. Our scheme can be applied to every rectangular QAM with the level higher than 64.

• Journal of the Korean Graphic Arts Communication Society
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• v.20 no.2
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• pp.57-68
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• 2002

It is required to estimate color reproduction accurately in printing. Because printing technology has been developing, and most people want to see the best color reproduction. Therefore many color reproduction methods, such as Neural Network, LUT(Look Up Table) have been proposed for a long time. However, these methods are required to measure a lot of samples of printing. In this paper, we propose a new method that prediction of color reproduction based on compensated Neugebauer model for dotgain. This method was significant to increase an accuracy of color prediction with simple process.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.307-310
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• 2002

Color reproductions in most ink jet printer are quite different from that of standard CRT (cathode ray tube) monitor display because of the nonlinear characteristic in subtractive color reproduction. Gray scale CCT(correlated color temperature) reproductions in a typical printer are vary with the input RGB level. A simple method for making constant gray scale CCT and gamma value in photo paper is proposed in this paper. The compensation of the CCT with white point of the photo paper under the CIE standard illuminant D65 and color correction has been confirmed using the LUT(look-up table) to compensate the CCT and gamma curve characteristic.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.301-302
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• 2006

Load effect which occurs due to the electrode structure for PDP(plasma display panel) can seriously reduce the image quality of PDP. In this paper, we propose the method of reducing load effect in presentation images, which have the possibility of load effect, by using LUT(look-up table). The proposed method enhances the image quality of PDP by correcting load effect region of the still image.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.407-418
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• 2014

As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.409-411
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• 2015

본 논문은 128/192/256-비트의 마스터키 길이를 지원하는 경량 블록 암호 알고리즘 CLEFIA-128/192/256의 FPGA 설계에 대하여 기술한다. 라운드키 생성을 위한 중간키 생성과 라운드 변환이 단일 데이터 프로세싱 블록으로 처리되도록 설계하였으며, 변형된 GFN(Generalized Feistel Network) 구조와 키 스케줄링 방법을 적용하여 데이터 프로세싱 블록과 키 스케줄링 블록의 회로를 단순화시켰다. Verilog HDL로 설계된 CLEFIA 크립토 프로세서를 FPGA로 구현하여 정상 동작함을 확인하였다. Vertex5 XC5VSX50T FPGA에서 1,563개의 LUT FilpFlop pairs로 구현되었으며, 최대 112 Mhz 81.5/69/60 Mbps의 성능을 갖는 것으로 예측되었다.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.997-1000
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• 2007

Achieving white balance is one of the key issues for LCD image quality enhancement. A well-known color correction algorithm is Accurate Color Capture (ACC). Determination of ACC correction values has been time consuming as past methods have required trial-and-error analysis of differences between predicted and measured values. We propose a new ACC value determination method that uses spatially emulated patterns and measured values on patterns.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.76-87
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• 1992

A novel self-organizing fuzzy plus PD control algorithm is proposed, where the proposed controller consists of a typical fuzzy reasoning part and self organizing part in which both on-line and off-line algorithms are employed to modify the Look-Up Table(LUT) for the fuzzy control rules and to decide how much fuzzy rules are to be modifid after evaluating the control performance, respectively. And the fuzzy controller is replaced by a PD controller in a prespecified region nearby the set point for good settling actions, where gain parameters are determined by fuzzy rules based on the magnitude of error velocity at the instant when the output penetrates into the prespecified region. To show the effectiveness of the proposed controller, extensive computer simulation results as well as experimental results are illustrated for an inverted pendulum system.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.47-48
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• 2007

This paper presents an efficient and simple hardware design of signal to noise ratio (SNR) estimator for DVB-S2 system. The estimator investigates the distribution of the received symbols by simply using two comparators and a counter, and calculates the address of an LUT where the corresponding SNR value is located. In this paper, we demonstrate the functional and timing simulation results of the FPGA implementation of proposed structure.