• Journal of Internet Computing and Services
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• v.21 no.2
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• pp.109-119
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• 2020

The FPGAs are semiconductors that can be redesigned after initial fabrication. It is used in various embedded systems such as signal processing, automotive industry, defense and military systems. However, as the complexity of hardware design increases and the design and manufacturing process globalizes, there is a growing concern about hardware trojan inserted into hardware. Many detection methods have been proposed to mitigate this threat. However, existing methods are mostly targeted at IC chips, therefore it is difficult to apply to FPGAs that have different components from IC chips, and there are few detection studies targeting FPGA chips. In this paper, we propose a method to detect hardware trojan by learning the static features of hardware trojan in LUT-level netlist of FPGA using machine learning.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.1-10
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• 1998

The advent of deep submicron technologies in the age of portable electronic systems creates a moving target for CAB algorithms, which now need to reduce power as well as delay and area in the existing design methodology. This paper presents a resynthesis algorithm for logic decomposition on mapped circuits. The existing algorithm uses a Huffman encoding, but does not consider glitches and effects on logic depth. The proposed algorithm is to generalize the Huffman encoding algorithm to minimize the switching activity of non-critical subcircuits and to preserve a given logic depth. We show how to obtain a transition-optimum binary tree decomposition for AND tree with zero gate delay. The algorithm is tested using SIS (logic synthesizer) and Level-Map (LUT-based FPGA lower power technology mapper) and shows 58%, 8% reductions on power consumptions, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.74-85
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• 2012

In this paper, we propose a optical property correction technique for a low-cost heterogeneous stereoscopic camera. Three main optical properties of a stereoscopic camera are zoom, focus, and DOF(depth of field). The difference or mis-match of these properties between two stereoscopic videos are the main causes of the visual fatigue to human eyes. The proposed correction technique reduces the difference of the optical properties between the stereoscopic videos and produces high-quality stereoscopic videos. To correct the zoom difference, a LUT(look-up table) is established to match the zoom ratio between the stereoscopic videos. To correct the DOF difference, the magnitude of image edge is measured and the lens iris is changed to control the DOF of the camera. A vertical-type stereoscopic rig is developed for the experiments of the optical property correction. Based on the experimental results, we find that a low-cost heterogeneous stereoscopic camera can be implemented, which can yield low visual fatigue to human eyes.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.798-803
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• 2005

This paper describes a design of AES(Advanced Encryption Standard)-based CCMP core for IEEE 802.1li wireless LAN security. To maximize its performance, two AES cores ate used, one is for counter mode for data confidentiality and the other is for CBC(Cipher Block Chaining) mode for authentication and data integrity. The S-box that requires the largest hardware in AES core is implemented using composite field arithmetic, and the gate count is reduced by about $20\%$ compared with conventional LUT(Lookup Table)-based design. The CCMP core designed in Verilog-HDL has 13,360 gates, and the estimated throughput is about 168 Mbps at 54-MHz clock frequency. The functionality of the CCMP core is verified by Excalibur SoC implementation.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2271-2280
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• 1999

In this paper, a variable motion estimation scheme based on HBMA(Hierarchical Block Matching Algorithm) to improve the performance and to reduce heavy computational and transmission load, is presented. The proposed algorithm is composed of four steps. First, block activity for each block is defined using the edge information of differential image between two sequential images, and then average block activity of the present image is found by taking the mean of block activity. Secondly, camera pan compensation is carried out, according to the average activity of the image, in the hierarchical pyramid structure constructed by wavelet transform. Next, the LUT classifying each block into one among Moving, No Moving, Semi-Moving Block according to the block activity compensated camera pan is obtained. Finally, as varying the block size and adaptively selecting the initial search layer and the search range referring to LUT, the proposed variable HBMA can effectively carries out fast motion estimation in the hierarchical pyramid structure. The cost function needed above-mentioned each step is only the block activity defined by the edge information of the differential image in the sequential images.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.4
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• pp.484-490
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• 2012

In this paper, we design a digitally pre-distorted RF power amplifier operating in 900 MHz band. The linearity of RF power amplifier is improved by employing the digital pre-distortion(DPD) based on affine projection(AP) algorithm, where the look-up table(LUT) method is used with non-linear indexing. The proposed DPD with AP algorithm is compared with that with normalized least mean square(NLMS) algorithm, applied to the RF power amplifier. A commercial power amplifier module is used for verification of the proposed algorithm which shows improvement of adjacent channel leakage ratio(ACLR) by about 21 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1248-1255
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2A
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• pp.148-158
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• 2008

This paper proposes an efficient signal to noise ratio (SNR) estimation algorithm and its hardware implementation for adaptive transmission system using M-ary modulation scheme. In this paper, we present the implementation results of the proposed algorithm for the second generation digital video broadcasting via satellite (DVB-S2) system, and the proposed algorithm can be tailored to the other communication systems using adaptive transmissions. We built a look-up table (LUT) using the theoretical background of the received signal distribution, and by using this LUT we need just two comparators and a counter for the hardware implementation. For this reason, the hardware of the proposed scheme produces accurate estimation results even with extremely low complexity. The simulation results investigated in this paper reveal that the proposed method can produce estimation results within the specified SNR range in the DVB-S2 system, and it requires a few hundreds of samples for average estimation error of about 1 dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.169-179
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• 2014

In this paper, we propose a DOF (Depth of Field) correction technique by determining the values of the internal parameters of a 3-D camera which consists of stereoscopic cameras of different optical properties. If there is any difference in the size or the depth range of focused objects in the left and right stereoscopic images, it could cause visual fatigue to human viewers. The object size of in the stereoscopic image is corrected by the LUT of zoom lenses, and the forward and backward DOF are corrected by the object distance. Then the F-numbers are determined to adjust the optical properties of the camera for DOF correction. By applying the proposed technique to a main-sub type 3-D camera using a GUI-based DOF simulator, the DOF of the camera is automatically corrected.