• Journal of Korea Multimedia Society
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• v.4 no.3
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• pp.257-269
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• 2001

Because of increasing number of integrated circuit, there is many tries of making chip of neural network and some chip is exit. but this is not prefer because YLSI technology can't support so large hardware. So imitation of whole system of neural network is more prefer. There is common procedure in signal processing as in the neural network and pattern recognition. That is multiplication of large amount of signal and reading LUT. This is identical with some operation of MLP, and need iterative and large amount of calculation, so if we make this part with hardware, overall system's velocity will be improved. So in this paper, we design neutral network, not neuron which can be used to many other fields. We realize this part by following separated bits addition method, and it can be appled in the real time parallel process processing.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.4
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• pp.304-310
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• 2017

In this paper, we propose the architecture of an IPM based lane detector for autonomous vehicles to detect and control the driving route along the curved lane. In the IPM image, we divide the area into two fields, Far/Near Field, and the lane candidate region is detected using the Hough transform to perform the matching for the curved lane. In autonomous vehicles, various algorithms must be embedded in the system. To reduce the system resources, we proposed a method to minimize the number of memory accesses to the image and various parameters on the external memory. The proposed circuit has 96% lane recognition rate and occupies 16% LUT, 5.9% FF and 29% BRAM in Xilinx XC7Z020. It processes Full-HD image at a rate of 42 fps at a 100 MHz operating clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.397-404
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• 2013

This paper propose the hardware architecture of face detection hardware system using the AdaBoost algorithm. The proposed structure of face detection hardware system is possible to work in 30frame per second and in real time. And the AdaBoost algorithm is adopted to learn and generate the characteristics of the face data by Matlab, and finally detected the face using this data. This paper describes the face detection hardware structure composed of image scaler, integral image extraction, face comparing, memory interface, data grouper and detected result display. The proposed circuit is so designed to process one point in one cycle that the prosed design can process full HD($1920{\times}1080$) image at 70MHz, which is approximate $2316087{\times}30$ cycle. Furthermore, This paper use the reducing the word length by Overflow to reduce memory size. and the proposed structure for face detection has been designed using Verilog HDL and modified in Mentor Graphics Modelsim. The proposed structure has been work on 45MHz operating frequency and use 74,757 LUT in FPGA Xilinx Virtex-5 XC5LX330.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1096-1101
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• 2004

The 3-D shape use to effect of movie, animation, industrial design, medical treatment service, education, engineering etc.... But it's not easy to make 3-D shape from the information of 2-D image. There are two methods in restoring 3-D video image through 2-D image; First the method of using a laser; Secondly the method of acquiring 3-D image through stereo vision. Instead of doing two methods with many difficulties, I figure out the method of simple 3-D image in this research paper. We present here a simple and efficient method, called direct calibration, which doesn't require any equations at all. The direct calibration procedure builds a lookup table(LUT) linking image and 3-D coordinates by a real 3-D triangulation system. The LUT is built by measuring the image coordinates of a grid of known 3-D points, and recording both image and world coordinates for each point; the depth values of all other visible points are obtained by interpolation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.10a
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• pp.499-503
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• 2000

The use of Multiple-Valued FFT(Fast fourier Transform) is extended from binary to multiple-valued logic(MVL) circuits. A multiple-valued FFT circuit can be implemented using current-mode CMOS techniques, reducing the transitor, wires count between devices to half compared to that of a binary implementation. For adder processing in FFT, We give the number representation using such redundant digit sets are called redundant positive-digit number representation and a Redundant set uses the carry-propagation-free addition method. As the designed Multiple-valued FFT internally using PD(positive digit) adder with the digit set 0,1,2,3 has attractive features on speed, regularity of the structure and reduced complexities of active elements and interconnections. for the mutiplier processing, we give Multiple-valued LUT(Look up table)to facilitate simple mathmatical operations on the stored digits. Finally, Multiple-valued 8point FFT operation is used as an example in this paper to illuatrates how a multiple-valued FFT can be beneficial.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.127-135
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• 2010

In motion adaptive temporal noise reduction filtering used for reducing video noises, the strength of motion adaptive temporal filtering should be carefully controlled according to temporal movement. This paper presents a motion adaptive temporal filtering scheme based on least-square training. Each pixel is classified to a specific class code according to temporal movement, and then, an iterative least-square training method is applied for each class code to find optimal filtering coefficients. The iterative least-square training is an off-line procedure, and the trained filter coefficients are stored in a lookup table (LUT). In actual noise reduction filtering operation, after each pixel is classified by temporal movement, simple filtering operation is applied with the filter coefficients stored in the LUT according to the class code. Experiment results show that the proposed method efficiently reduces video noises without introducing blurring.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.190-196
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• 2014

This paper proposes a mobile-optimized pedestrian detection method using Cascade of HOG(Histograms of Oriented Gradients) for ADAS(Advanced Driver Assistance System) on smartphones. In order to use the limited resource of mobile platforms efficiently, the method is implemented by the OpenCL(Open Computing Language) library, and its processing time is reduced in the following two aspects. Firstly, the method sets a program build option specifically and adjusts work group sizes as variety of kernels in the host code. Secondly, it utilizes local memory and a LUT(Look-Up Table) in the kernel code to accelerate the program. For performance evaluation, the developed algorithm is compared with the mobile CPU-based OpenCV(Open Computer Vision) for Android function. The experimental results show that the processing speed is 25% faster than the OpenCV hogcascade.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.912-918
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• 2014

In this paper, a VHF band multi channel phase discriminator for direction finding equipment using tripple baseline interferometer technique is proposed. In order to measure simultaneously phase difference between IF(Intermediate Frequency) signals of the direction finding equipment, phase discriminator was designed to have parallel structure with multi channel, the phase correlator of phase discriminator was designed with I, Q mixer for reducing number of components. And digital LUT(Look Up Table) was applied for compensating error of phase discriminator due to phase unbalance of RF components. The measured phase accuracy of fabricated phase discriminator was 2 degree RMS(Root Mean Square) at 30 dB SNR condition, which is superior to the phase accuracy of conventional product.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1109-1115
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• 2010

FMCW(Frequency Modulation Continuous Wave) Radar can detect the distance and the velocity of forward obstacles using linearly modulated FM signal. For better performance, the RF of radar should be operated with wideband frequency linearity on 300 MHz bandwidth at 77 GHz carrier frequency. In this paper, we propose a simple method for improving frequency linearity of FMCW radar implemented with VCO. The proposed method shows that the Voltage-Frequency relation of VCO could be measured by using the modified Tx waveform of FMCW radar. Then the measured nonlinearity could be compensated using LUT(Look-up Table) with easy. It is noted that the proposed can be adopted in existing system without extra circuit.

• Journal of Internet Computing and Services
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• v.21 no.2
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• pp.109-119
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• 2020

The FPGAs are semiconductors that can be redesigned after initial fabrication. It is used in various embedded systems such as signal processing, automotive industry, defense and military systems. However, as the complexity of hardware design increases and the design and manufacturing process globalizes, there is a growing concern about hardware trojan inserted into hardware. Many detection methods have been proposed to mitigate this threat. However, existing methods are mostly targeted at IC chips, therefore it is difficult to apply to FPGAs that have different components from IC chips, and there are few detection studies targeting FPGA chips. In this paper, we propose a method to detect hardware trojan by learning the static features of hardware trojan in LUT-level netlist of FPGA using machine learning.