• IEMEK Journal of Embedded Systems and Applications
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• v.15 no.6
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• pp.289-297
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• 2020

Although flash disks are being used widely instead of hard disks, it is difficult to optimize for effective utilization of flash disks because overwrite in place is impossible and the power consumption and time required for read, write, and erase operations are all different. One of these optimization issues is a cache management strategy to minimize write operations. The cache operates at two levels: an operating system equipped with flash disks and a translation layer within the flash disk. Most studies deal with the operating system-level cache strategy. In this study, we implement and analyse the DPW-LRU algorithm which is one of the recently proposed operating system cache replacement algorithms to apply to FTL, and grope with some improvements. As a result of the experiment, the DPW-LRU algorithm maintained superiority even in the FTL environment, and showed better performance with a slight improvement.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.109-116
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• 2018

SSDs that are not allowed in-place update within the allocated page cause another allocation of a new page that will replace the previous page at the moment data modification occurs. This intrinsic characteristic of SSDs requires many changes to the existing HDD-based IO theory. In this paper, we conduct a performance comparison of FTL caching strategy in perspective of cache hashing (Global vs. grouped) and caching algorithm (LRU vs. NUR) through a simulation. Experimental results show that in terms of energy consumption for flash operation the grouped management of cache is not suitable and NUR algorithm is superior to LRU algorithm. In particular, we found that the cache hit ratio of LRU algorithm is about 10% point higher than that of NUR algorithm while the energy consumption of LRU algorithm is about 32% high.

• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.11-17
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• 2020

In this paper, we propose practical results for cache replacement policy by measuring cache hit and search time for each replacement algorithm through cache simulation. Thus, the structure of each cache memory and the four types of alternative policies of FIFO, LFU, LRU and Random were implemented in software to analyze the characteristics of each technique. The paper experiment showed that the LRU algorithm showed hit rate and search time of 36.044% and 577.936ns in uniform distribution, 45.636% and 504.692ns in deflection distribution, while the FIFO algorithm showed similar performance to the LRU algorithm at 36.078% and 554.772ns in even distribution and 45.662% and 489.574ns in bias distribution. Then LFU followed, Random algorithm was measured at 30.042% and 622.866ns at even distribution, 36.36% at deflection distribution and 553.878ns at lowest performance. The LRU replacement method commonly used in cache memory has the complexity of implementation, but it is the most efficient alternative to conventional alternative algorithms, indicating that it is a reasonable alternative method considering the reference information of data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.849-858
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• 2012

We proposed a scheme to accurately detect elephant flows. Along the ever increasing traffic trend, certain flows occupy the network heavily in terms of time and network bandwidth. These flows are called elephant flows. Elephant flows raises complicated issues to manage for Internet traffics and services. One of the methods to identify elephant flows is the Landmark LRU cache scheme, which improved the previous method of Least Recently Used scheme. We proposed a cache update algorithm, to further improve the existing Landmark LRU. The proposed scheme improves the accuracy to detect elephant flow while maintaining efficiency of Landmark LRU. We verified our algorithm by simulating on Sangmyung University's wireless real network traces and evaluated the improvement.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.5
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• pp.529-539
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• 2000

This paper proposes a prefetch-based disk buffer management algorithm, which we call W2R (Veighingjwaiting Room). Instead of using elaborate prefetching schemes to decide which blockto prefetch and when, we simply follow the LRU-OBL (One Block Lookahead) approach and prefetchthe logical next block along with the block that is being referenced. The basic difference is that theW2R algorithm logically partitions the buffer into two rooms, namely, the Weighing Room and theWaiting Room. The referenced, hence fetched block is placed in the Weighing Room, while theprefetched logical next block is placed in the Waiting Room. By so doing, we alleviate some inherentdeficiencies of blindly prefetching the logical next block of a referenced block. Specifically, a prefetchedblock that is never used may replace a possibly valuable block and a prefetched block, thoughreferenced in the future, may replace a block that is used earlier than itself. We show through tracedriven simulation that for the workloads and the environments considered the W2R algorithm improvesthe hit rate by a maximum of 23.19 percentage points compared to the 2Q algorithm and a maximumof 10,25 percentage feints compared to the LRU-OBL algorithm.

• Korean Management Science Review
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• v.31 no.3
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• pp.61-76
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• 2014

There are three methods for calculating the optimal level for spare part inventories in a MIME (Multi Indenture and Multi Echelon) system : marginal analysis, Lagrangian relaxation method, and genetic algorithm. However, their solutions are sub-optimal solutions because the MIME system is neither convex nor separable by items. To be more specific, SRUs (Shop Replaceable Units) are required to fix a defected LRU (Line Replaceable Unit) because one LRU consists of several SRUs. Therefore, the level of both SRU and LRU cannot be calculated independently. Based on the limitations of three existing methods, we proposes a improved algorithm applying marginal analysis on determining LRU stock level and genetic algorithm on determining SRU stock level. It can draw optimal combinations on LRUs through separating SRUs. More, genetic algorithm enables to extend the solution search space of a SRU which is restricted in marginal analysis applying greedy algorithm. In the numerical analysis, we compare the performance of three existing methods and the proposed algorithm. The research model guarantees better results than the existing analytical methods. More, the performance variation of the proposed method is relatively low, which means one execution is enough to get the better result.

• Journal of KIISE
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• v.41 no.11
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• pp.871-877
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• 2014

Cache replacement algorithms have been developed in order to reduce miss counts. In modern processors, the performance gap between the processor and main memory has been increasing, creating a more important role for cache replacement policies. The Least Recently Used (LRU) policy is one of the most common policies used in modern processors. However, recent research has shown that the performance gap between the LRU and the theoretical optimal replacement algorithm (OPT) is large. Although LRU replacement has been proven to be adequate over and over again, the OPT/LRU performance gap is continuously widening as the cache associativity becomes large. In this study, we observed that there is a potential chance to improve cache performance based on existing LRU mechanisms. We propose a method that enhances the performance of the LRU replacement algorithm based on the access proportion among the lines in a cache set during a period of two successive replacement actions that make the final replacement action. Our experimental results reveals that the proposed method reduced the average miss rate of the baseline 512KB L2 cache by 15 percent when compared to conventional LRU. In addition, the performance of the processor that applied our proposed cache replacement policy improved by 4.7 percent over LRU, on average.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.5
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• pp.9-13
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• 2023

Multimedia streaming data is very large in size and accessed sequentially, making the LRU(Least Recently Used) algorithm widely used to improve I/O performance in traditional caching environments ineffective. Experimental analysis of this has shown the superiority of interval-based caching over LRU, but the theoretical basis has not been proven. In this paper, we design a cache performance model to analyze the optimality of caching for multimedia streaming environments and design a theoretically optimal caching algorithm based on interval caching. Then, we show that the algorithm we design is an optimal algorithm that minimizes cache misses of streaming data based on the proposed model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.2
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• pp.178-188
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• 2016

The traffic in the wired and wireless networks has increased exponentially because of increase of smart phone and improvement of PC performance. Multimedia services and file transmission such as Facebook, Youtube occupy a large part of the traffic. CDN is a technique that duplicates the contents on a remote web server of content provider to local CDN servers near clients and chooses the optimal CDN server for providing the content to the client in the event of a content request. In this paper, the content request message between CDN servers and the client used the SCRP algorithm utilizing the MST algorithm and the traffic throughput was optimized. The average response time for the content request is reduced by employing HC_LRU cache algorithm that improves the cache hit ratio. The proposed SCRP and HC_LRU algorithm may build a scalable content delivery network system that efficiently utilizes network resources, achieves traffic localization and prevents bottlenecks.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.634-641
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• 2006

Flash memory has many advantages like non-volatility and fast I/O speed, but it has also disadvantages such as not-in-place-update data and asymmetric read/write/erase speed. For the performance of flash memory storage, it is essential for the buffer replacement algorithms to reduce the number of write operations that also affects the number of erase operations. A new buffer replacement algorithm is proposed in this paper, that delays the writes of not-cold-dirty pages in the buffer cache of flash storage. We show that this algorithm effectively decreases the number of write operations and erase operations without much degradation of hit ratio. As a result overall performance of flash I/O speed is improved.