• Journal of the Korea Society of Computer and Information
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• v.25 no.2
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• pp.21-29
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• 2020

The use of NAND flash memory is continuously increased with the demand of mobile data in the IT industry environment. However, the erase operations in flash memory require longer latency and higher power consumption, resulting in the limited lifetime for each cell. Therefore, frequent write/erase operations reduce the performance and the lifetime of the flash memory. In order to solve this problem, management techniques for improving the performance of flash based storage by reducing write and erase operations of flash memory with using disk buffers have been studied. In this paper, we propose a CPWL to minimized the number of write operations. It is a disk buffer management that separates read and write pages according to the characteristics of the buffer memory access patterns. This technique increases the lifespan of the flash memory and decreases an energy consumption by reducing the number of writes by arranging pages according to the characteristics of buffer memory access mode of requested pages.

• Journal of KIISE:Databases
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• v.28 no.4
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• pp.688-701
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• 2001

Web caching has become an important problem addressing the performance issues in web applications. In this paper we propose a method that enhances the performance of web caching by incorporating the expiration time of web data we introduce the notion of the effective reference probability that incorporates the effect of expiration time into the reference probability used in the existing cache replacement algorithms .We formally define the effective reference probability and derive it theoretically using a probabilistic model. By simply replacing probabilities with the effective reference probability in the existing cache replacement algorithms we can take the effect of expiration time into account The results of performance evaluation through experiments show that the replacement algorithms using the effective reference probability always outperform the existing ones. The reason is that the proposed method precisely reflects the theoretical probability of getting the cache effect, and thus, incorporates the influence of the expiration time more effectively. In particular when the cache fraction is 0.05 and data update is comparatively frequent (i.e. the update frequency is more than 1/0 of the reference frequency) the performance enhancement is more than 30% in LRU-2 and 13% in Aggarwal's method (PSS integrating a refresh overhead factor) The results show that effective reference probability contributes significantly to the performance enhancement of the web cache in the presence of expiration time.

• Journal of the Korea Society of Computer and Information
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• v.10 no.6 s.38
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• pp.153-166
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• 2005

Existing single cache structure has shown difference of hit-ratio according to individually replacement strategy However. It needs new improved cache structure for reducing network traffic and providing advanced hit-ratio. Therefore, this Paper design push agent model using dual cache for increasing hit-ratio by reducing server overload and network traffic by repetition request of persistent and identical information. In this model proposes dual cache structure to do achievement replace gradual cache using by two caches storage space for reducing server overload and network traffic. Also, we show new cache replace techniques and algorithms which executes data update and delete based on replace strategy of Log(Size) +LRU, LFU and PLC for effectiveness of data search in cache. And through an experiment, it evaluates Performance of dual cache push agent model.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.72-79
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• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• The Journal of the Korea Contents Association
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• v.10 no.3
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• pp.64-71
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• 2010

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.25-32
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• 2014

In this paper, we proposed a partial-way set associative cache memory with an effective memory access time and low energy consumption. In the proposed set-associative cache memory, it is allowed to access only a 2-ways among 4-way at a time. Choosing ways to be accessed is made dynamically via the least significant two bits of the tag. The chosen 2 ways are sequentially accessed by the way selection bits that indicate the most recently referred way. Therefore, each entry in the way has an additional bit, that is, the way selection bit. In addition, instead of the 4-way LRU or FIFO algorithm, we can utilize a simple 2-way replacement policy. Simulation results show that the energy*delay product can be reduced by about 78%, 14%, 39%, and 15% compared with a 4-way set associative cache, a sequential-way cache, a way-tracking cache, and a way cache respectively.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.11a
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• pp.1728-1731
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• 2010

가상화는 서버통합을 통하여 가상머신 간의 하드웨어 자원을 공유함으로써, 총 소유 비용을 줄일 수 있어서 널리 사용되고 있다. 하지만 메모리는 다른 장치와 달리 쉽게 공유되기 어려워서 서버 통합에 있어서 병목이 되고 있다. 이를 해결하기 위한 여러가지 방법들중 많은 방법이 공통적으로 가상머신모니터에서 페이징을 사용하고 있다. 하지만 게스트 운영체제와 가상머신모니터가 모두 페이징을 할 경우, 페이징이 급격히 증가가는 이중 페이징 문제가 발생할 수 있다. 본 논문에서는 이중 페이징 문제를 해결하기 위한 방법으로 가상머신모니터와 게스트 운영체제가 스왑 장치를 공유하는 가상화 지원 스왑 장치를 제안한다. 또한 실험을 통하여 가상머신모니터가 페이지 교환 알고리즘으로 LRU 를 사용할 경우 이중 페이징 문제가 크게 발생할 수 있음을 보인다.

• The KIPS Transactions:PartD
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• v.18D no.1
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• pp.1-8
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• 2011

The cache structure, which is designed for assuring fast accesses to frequently accessed data, resides on the various levels of computer system hierarchies. Many studies on this cache structure have been conducted and thus many page-replacement algorithms have been proposed. Most of page-replacement algorithms are designed on the basis of heuristic methods by using their own criteria such as how recently pages are accessed and how often they are accessed. This data-retrieval process in computer systems is analogous to human memory retrieval process since the retrieval process of human memory depends on frequency and recency of the retrieval events as well. A recent study regarding human memory cognition revealed that the possibility of the retrieval success and the retrieval latency have a strong correlation with the frequency and recency of the previous retrieval events. In this paper, we propose a novel page-replacement algorithm by utilizing the knowledge from the recent research regarding human memory cognition. Through a set of experiments, we demonstrated that our new method presents better hit-ratio than the LRFU algorithm which has been known as the best performing page-replacement algorithm for DBMS caches.

• Journal of Internet Computing and Services
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• v.16 no.5
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• pp.19-27
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• 2015

Due to the advantages of fast read/write operation and low power consumption, SSD(Solid State Drive) is now widely adopted as storage device of smart phone, laptop computer, server, etc. However, the shortcomings of SSD such as limited number of write operations and asymmetric read/write operation lead to the problem of shortened life span of SSD. Therefore, the block replacement policy of SSD used as cache for HDD is very important. The existing solutions for improving the lifespan of SSD including the LARC scheme typically employ the LRU algorithm to manage the SSD blocks, which may increase the miss rate in SSD due to the replacement of frequently used block instead of rarely used block. In this paper we propose a novel block replacement scheme which considers the block reuse interval to effectively handle various data read/write patterns. The proposed scheme replaces the block in SSD based on the recency decided by reuse interval and age along with hit ratio. Computer simulation using workload trace files reveals that the proposed scheme consistently improves the performance and lifespan of SSD by increasing the hit ratio and decreasing the number of write operations compared to the existing schemes including LARC.

• Journal of KIISE:Software and Applications
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• v.28 no.4
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• pp.369-379
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• 2001

본 논문은 부영역 분할과 코드워드 인텍스의 캐시 개념을 이용하여 벡터 양자화를 위한 고속코드북 생성 및 부호화 방법을 제안한다. 제안한 방법은 인접한 입력 벡터는 대개 코드북내 특정 코드워드에 의해 나타내어지는 국부성에 바탕을 두고 있다. 초기에 모든 학습 벡터가 거리에 기반한 근접성을 이용하여 정해진 수의 부영역으로 분할된다. 각 부영역에 하나의 코드워드 인덱스 캐시가 할당되는데 이 캐시는 학습 초기에는 전체 코드북 크기에 대응하는 코드워드 인덱스를 갖는다. 학습이 진행되면서 입력 벡터가 갖는 국부성 때문에 각 부영역내 캐시중 사용되지 않는 코드워드 인덱스가 점차 발생하게 되므로 이들은 LRU(Least Recently Used) 삭제 알고리즘에 의해 제거된다. 학습이 진행됨에 따라 부영역 캐시에는 주어진 입력 벡터에 의해 참조되는 코드워드 인덱스만이 남게 되므로 한 학습 주기 동한 필요한 학습 시간이 점차 짧아지게 되어 전체적으로 코드북 생성 시간을 크게 줄일 수 있게 된다. 제안한 방법은 매 학습주기마다, 코드워드 인덱스 삭제 후보 중 주어진 부영역 중심으로부터 거리에 의해 멀리 떨어진 것부터 반만을 제거함에 따라. 복원된 영상의 화질 열화가 거의 없다. 시뮬레이션 결과 제안한 방법은 기존의 LBG 방법에 비해 화질 열화는 거의 없지만 코드북 생성 (또는 부호화) 속도를 2.6-5.4배 (또는3.7-18.8배) 향상시킨다.