• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.10C
• /
• pp.923-929
• /
• 2003

Turbo processing have been known as methods close to Shannon limit in the aspect of wireless multi-input multi-output (MIMO) communications similarly to wireless single antenna communication. The iterative processing can maximize the mutual effect of coding and interference cancellation, but LDPC coding has not been used for turbo processing because of the inherent decoding process delay. This paper suggests a LDPC coded MIMO system with turbo parallel space-time (Turbo-PAST) processing for high-speed wireless communications and proposes a average soft-output syndrome (ASS) check scheme at low signal to noise ratio (SNR) for the Turbo-PAST system to decide the reliability of decoded frame. Simulation results show that the suggested system outperforms conventional system and the proposed ASS scheme effectively reduces the amount of turbo processing iterations without performance degradation from the point of average number of iterations.

• Proceedings of the Korean Information Science Society Conference
• /
• 2006.06d
• /
• pp.250-252
• /
• 2006

ALC(Asyncronous Layered Coding)는 LCT(Layered Coding Transport)기반의 폭넓은 확장성과 다양한 전송속도로 신뢰성 있는 멀티캐스트 전송을 주 목적으로 한다. ALC는 다른 RMT 프로토콜과는 달리 재전송을 하지 않고 receiver-driven 형태의 혼잡제어를 하기 때문에 신뢰성을 제공하기 위해 FEC(Forward Error Correction) 스킴를 이용한다. 본 논문은 신뢰적인 멀티캐스트 전송 프로토콜을 위해 ALC와 FEC 스킴 중 하나인 LDPC 코드를 이용하여 구현한다. 인코딩 비율(Encoding ratio)에 따라 일정 수준 이상의 복구 성공 확율에 대해 최대 허용 가능한 패킷 손실률을 측정하여 신뢰치를 측정한다. 마지막으로 일대다의 파일 전송 시, TCP와 비교하여 본 구현물의 유연성과 효율성에 대해 분석 및 평가한다.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2006.07a
• /
• pp.491-491
• /
• 2006

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.2271-2272
• /
• 2008

Recently, LDPC codes received a lot of attention in 4G. LDPC codes perform good error correction at high SNR. But LDPC codes are complex design and not good at low SNR. At low SNR, convolution codes and turbo codes show more good performance than LDPC codes. The main subject presented in this study is that parallel encoding and decoding according to SNR. The system chooses convolution codes at low SNR and chooses LDPC codes at high SNR.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.17 no.3
• /
• pp.63-69
• /
• 2017

In next generation satellite broadcasting system, requirement of high throughput efficiency has been increasing continuously. To increase throughput efficiency and improve bit error performance simultaneously, FTN method and LDPC codes are employed in new sattelite standard, DVB-S3 system. This paper considered three kinds of methods for increase throughput efficiency. Firstly, as conventional one, high coding rate parity matrix in LDPC encoder is considered. Secondly, punctured coding scheme which delete the coded symbols according to appropriate rules is considered. Lastly, FTN method which transmit fater than Nyquist rate is considered. Among of three kinds of methods, FTN method is most efficient in aspect to performance while maintain same throughput efficiency.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.38A no.8
• /
• pp.662-668
• /
• 2013

Mobile communication systems have been adopting link adaptive transmission schemes such as adaptive modulation and coding (AMC) and hybrid-ARQ (HARQ). Incremental redundancy (IR) HARQ scheme is known to be highly efficient in terms of throughput and power consumption and can be a good solution for mobile communication systems. In this paper, we propose an IR-HARQ scheme based on dual-diagonal parity-type block LDPC codes in which we define a transmission priority of coded bits and propose the sub-packet construction rule. We present the throughput performance of IR-HARQ with various modulation and coding and multi-antenna modes. Consequently, the proposed scheme provides the improvement of system throughput by elaborate link adaptation with CQI information.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.118-124
• /
• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.9 s.351
• /
• pp.31-37
• /
• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Journal of Satellite, Information and Communications
• /
• v.10 no.3
• /
• pp.73-77
• /
• 2015

In this paper, we present two simulation methods to investigate the effect of excluding bit errors on generating the extrinsic information transfer (EXIT) chart for low density parity check (LDPC) and turbo codes. We utilized the simulation methods including and excluding bit errors to generate EXIT chart which was originally proposed for turbo codes. The generated EXIT charts for LDPC and turbo codes shows that the presented methods appropriately demonstrates the performance behaviours of iterative decoding for LDPC and turbo codes. Analysis on the simulation results demonstrates that the EXIT chart excluding the bit errors shows only a small part of the curves where the amount of information is too large.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.30 no.6C
• /
• pp.434-441
• /
• 2005

For LDPC decoding, received symbols are splitted bit by bit based using the received in-phase and quadrature components. The method of bit-splitting is affected on decoding performance because its method depend on distance over symbol constellation. Therefore this paper propose the bit split method using the sector information with sacrifice a little performance loss compared to Euclidean distance method. Futhermore DVB-S2 specification supports BC(Backward Compactible) mode which using the hierarchical modulation method, this paper also analyze the decoding performance according to deviation angle of 8PSK constellation for various LDPC coding rates.