• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.451-456
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• 2021

In order to improve the cell capacitance and scale down in capacitors of semiconductor memory devices, a stacked ONO structure has been introduced as a dielectric layer and thinning of these layers has been attempted continuously. However, many problems have emerged in the manufacturing process. In this study, L/L LPCVD system was used to suppress the growth of natural oxide film of about 10 Å, which was able to secure the capacitance of 3fF / cell. In addition, we investigated the effect of thinning of the dielectric film on the abnormal oxidation of the nitride film, and proposed a stable process control method for forming the dielectric film to ensure oxidation resistance.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.5
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• pp.791-796
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• 2017

In this study, we investigated the influence of the fabrication process of stacked capacitors on the cell capacitance by using Load Lock (L/L) LPCVD system for dielectric thin film of DRAM capacitor. As a result, it was confirmed that the capacitance difference of about 3-4 fF is obtained by reducing the effective thickness of the oxide film by about $6{\AA}$ compared to the conventional non-L/L device. In addition, Cs was found to be about 3-6 fF lower than the calculated value, even though the measurement range of the thickness of the nitride film as an insulating film was in a normal management range. This is because the node poly FI CD is managed at the upper limit of the spec, resulting in a decrease in cell surface area, which indicates a Cs reduction of about 2fF. Therefore, it is necessary to control the thickness of insulating film and CD management within 10% of the spec center value in order to secure stable Cs.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.429-432
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• 1987

A new LOCOS (Local Oxidation of Silicon) process using a thin nitride film directly deposited on the silicon substrate by LPCVD has been developed in order to reduce the bird's beak length. SEM studies showed that nitride thickness of 50nm can decrease the bird's beak length down to 0.2um with 450nm field oxide. No crystalline defects are observed around the bird's beak after the Wright etch. A 30% improvement in current density was obtained when this new method was applied to MOS transistors (W/L*2.9/20.4) compared to conventional LOCOS process (bird's beak length=0.7um). Other various electrical parameters improved by this new simple LOCOS process are reported in this paper.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.67-72
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• 1989

Room Temperature Plasma Nitridation of silicon was investigated as a new LOCOS (local oxidation of silicon) process in order to reduce the bird's beak length. In $N_2$ plasma formed by 100kHz, 400W AC power, a thin silicon nitride film (<100${\AA}$) was uniformly grown on a silicon substrate. SEM studies showed that the nitride layer formed by this method can effectively protect the silicon from oxidation and reduce the bird's beak length to $0.2{mu}m$ when 4000${\AA}$ field oxide is grown. This is a considerable improvement comparing with 0.7${mu}m,$ the bird's beak, for the conventional LOCOS process using a thick LPCVD nitride. No appreciable crystalline defect could be found around the bird's beak with SEM cross-section afrer Secco etch. Leakage current tests were carried out on the $N^+/P^-$ well and $P^+/N^-$ well diodes formed by this new LOCOS process. The electrical tests indicate that this new process has electrical properties similar or superior to those of the conventional LOCOS process.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.107-107
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• 2003

원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 100%에 가까운 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 특히 반도체의 logic 및 memory 소자의 gate 공정에서 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는 silicon oxide 박막에 적용될 경우, LPCVD 방법에 비해 낮은 온도에서 증착이 가능해 boron과 같은 dopant들의 확산을 최소화하여 transistor 특성 향상이 가능하며, PECVD 방법에 비해 전기적·물리적 특성이 월등히 우수하고 대면적 uniformity 증가가 기대된다. 본 연구에서는 자체적으로 설계 및 제작한 장비를 이용하여 silicon oxide 박막을 ALD 방법으로 증착하고 그 특성을 살펴보았다. 먼저, cycle 수에 따른 증착 박막 두께의 linearity를 통해서 원자층 증착(ALD)임을 확인할 수 있었으며, reactant exposure(L)와 증착 온도에 따른 deposition rate 변화를 알아보았다 Elipsometer를 이용해 증착된 silicon oxide 박막의 두께 및 굴절률과 그 uniformity를 관찰하였고, AES 및 XPS 분석 장비로 박막의 조성비와 불순물 성분을 살펴보았으며, 증착 박막의 치밀성 평가를 위해 HF etchant로 wet etch rate를 측정하여 물리적 특성을 정리하였다. 특히, 기존의 박막 증착 방법인 LPCVD와 PECVD에 의한 silicon oxide박막의 물성과 비교, 평가해 보았다. 나아가 적절한 촉매 물질을 선정하여 원자층 증착(ALD) 공정에 적용하여 그 효과도 살펴보았다.

• Korean Journal of Materials Research
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• v.7 no.2
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• pp.102-106
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• 1997

Micro gas sensors including thin film catal) tic type require stress-free memhrancs for etch stop of Si anisotropic etching and sublayer of sensing elements hecause stress is one of the main factors affecting breakdown of thin membranes. This paper reports the effects of deposition conditions on stress and refractive index of $SiN_{x}/SiO_{x}/(NON)$ films deposited by low pressure c11ernic;rl vapor deposition(L, t'CVI)) 2nd reactve sputtering. In the case of I.PCVI1, the stresses of $SiN_{x}$ and NON films arc $7.6{\times}10^{8}dyne/cm^2$ and $3.3{\times}10^{8}dyne/cm^2$, respectibely, and the refractive indices are 3.05 and 152, respectively. In the cxse oi the sputtered SiN, , compressi\e stress decreased in magnitude and then turned to tensility as increasing proc, ess pressure by lmtorr to 30mtorr and cicreasmg applied power density by $2.74W/cm^2$ to $1.10W/cm^2$. The hest value of film stress obt;~ined under condition of lOmtorr and $1.37W/cm^2$ in this' experiment was $1.2{\times}10^{9}dyne/cm^2$ cnnipressive. The refr~ict~ve index decreased from 2 05 to 1 89 as decreasing applied power density by lnitorr to 3Orntorr and increasing process pressure hy $2.74W/cm^2$ to $1.10W/cm^2$. Stresses of films deposited by both LPCVL) and sputtering decreased as incre;lsing temperature and showed plastic behavior as decreasing temperature.

• Korean Journal of Materials Research
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• v.4 no.6
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• pp.662-668
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• 1994

The physical and electrical characteristics of sub-l0nm thick capacitor dielectrics formed by wet oxidation of silicon nitride(oxide/nitride composite) and by removing the top oxide of oxidized silicon nitride(0xynitride) are described. For the capacitors with an oxide/nitride composite layer, the capacitance decreases sharply, but the breakdown field increases with an increase in the wet oxidation time at $900^{\circ}C$. For the capacitors with oxynitride layers, the values of both the capacitance and the breakdown field increase with increasing wet oxidation time. The reduction of effective thickness and the improved quality of oxynitride film are responsible for the improved capacitance and increased breakdown fields, respectively. In addition, intrinsic TDDB characteristics and early breakdown failure rate of oxynitride film are improved with increasing oxidation time. Consequently, the oxynitride film is suitable for dynamic memories as a thin dielectric film.

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.114-119
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• 2004

Silicon Nitride thin films were deposited on p-type Si (100) substrates by atomic layer deposition (ALD) method at $550^{\circ}C$ using alternating exposures of $SiH_2Cl_2$ and $NH_3$, and the physical and electrical propeties of the deposited films were characterized. The thickness of the films was linearly increased with the number of deposition cycles, and the growth rate of the films was 0.13 nm/cycle with the reactant exposures of $3.0\times10^{9}$ L. The silicon nitride thin films deposited by Alf exhibited similar physical properties with the silicon nitride thin films deposited by low-pressure chemical vapor deposition (LPCVD) method in terms of refractive index and wet etch rate, lowering deposition temperature by more than 200 $^{\circ}C$. The ALD films showed the leakage current density of 0.79 nA/$\textrm{cm}^2$ at 3 MV/cm, which is lower than 6.95 nA/$\textrm{cm}^2$ of the LPCVD films under the same condition.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.115-123
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• 1999

A micro-gas sensor with heater and sensing electrode on the same plane was fabricated on phosphosilicate glass(PSG, 800nm)/$Si_3N_4$ (150nm) dielectric membrane. PSG film was provided by atmospheric pressure chemical vapor deposition(APCVD), and $Si_3N_4$ film by low pressure chemical vapor deposition (LPCVD). Total area of the fabricated device was $3.78{\times}3.78mm^2$. The area of diaphragm was $1.5{\times}1.5mm^2$, and that of the sensing layer was $0.24{\times}0.24mm^2$. Finite-element simulation was employed to estimate temperature distribution for a square-shaped diaphragm. The power consumption of Pt heater was about 85mW at $350^{\circ}C$. Tin thin films were deposited on the silicon substrate by thermal evaporation at room temperature and $232^{\circ}C$, and tin oxide films($SnO_2$) were prepared by thermal oxidation of the metallic tin films at $650^{\circ}C$ for 3 hours in oxygen ambient. The film analyses were carried out by SEM and XRD techniques. Effects of humidity and ambient temperature on the resistance of the sensing layer were found to be negligible. The fabricated micro-gas sensor exhibited high sensitivity to butane gas.