• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.8 s.350
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• pp.91-96
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• 2006

High efficiency switching mode circuits such as class I amplifiers have been well known in the MHz frequency range. The class E amplifier is a type of switching mode amplifier offering very high efficiency approaching 100%. In this paper, the class E amplifier has been designed by using the harmonic balance method of circuit simulator. The designed amplifier is realized by using pHEMT and microstrip line, shows 66% power added efficiency (PAE) at 2.4GHz with 17.6dBm output power. With -3dBm input power of wireless LAN, measured output spec01m can meet the required IEEE 802.11g standard spectrum mask. That means the required amplifier back off of 9dB from $P_{ldB}$ to satisfy the required wireless LAN spectrum mask.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.38 no.4
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• pp.59-71
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• 2001

The Current CORBA shows some limitations for its successful deployment in real time system applications. Recently, OMG adopted Real-Time CORBA specification, which is defined as an extension to CORBA. The goal of the Real-Time CORBA is to provide a standard for CORBA ORB implementations that support 'end to end predictability'. In order to support 'end-to-end predictability', Real Time CORBA specifies many components such as priority model, communication protocol configuration, thread management, and etc. Among them, 'priority model' is the most important mechanism for avoiding or bounding priority inversion in CORBA invocations. In this paper, we present our efforts on a design ,and implementation of the Priority Model in Real-Time CORBA specification. The implementation is done as an extension of omniORB2(v.3.0.0), a popular open source non real time ORB. Experiment results demonstrate that our priority model implementation shows better performance and predictability than the non real-time ORB.

• Fashion & Textile Research Journal
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• v.17 no.3
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• pp.447-461
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• 2015

The purpose of this study is to develop a torso pattern that is highly representative for the proper body shape of women in their thirties. Size data of the women with age of 30 through 39 from the database of Size Korea 2004 were used for the study. In order to develop a master pattern which will be used as the benchmark for grading of research group, 4 existing torso block drafting methods were compared based on the data gathered and the block with the highest evaluation score was utilized as a reference point. For the analysis, data was divided into four types, only the data of 138 subjects which were evaluated at least by four or more experts as valid were used for the study. The major results can be summarized as follow. The women of bust girth of 91cm and height of 160cm which was turned out to be representative type of research group were used as standard measurement for the purpose of reflecting not only curve length of the 3D analysis measurement but also the difference between front and back thickness to the pattern. Dart locations were set based on front and back torso ease, shoulder area revisions, front sagging length 1.5cm and cross section crevice length analysis. According to the experts' appearance evaluation of the pattern was found to be better than the control pattern which was regarded as the best among 4 patterns created based on existing torso block drafting methods.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
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• v.23 no.3
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• pp.183-190
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• 2017

Carton clamp truck is widely perceived as the high-efficient handling equipment of factory premises and warehouse by its capability of palletless handling. Therefore, the significance of a lab-based handling simulation is becoming higher with the growth of clamp truck usage. In this study, preliminary FEA and design of handling test courses for the lab-based simulation of carton clamp truck handling were performed, and the PSD analyses were performed for the modified one for the test course proposed by Park et al. (2017) as well as ASTM D 6055 and ISTA 3B standards. For the vibration in all directions, the vibration energy intensity analyzed by ISTA 3B standard showed higher than that by the other two cases. A FEA was performed for the handling operation of the sudden stop of the clamps after lifting the target HCP (heavyweight refrigerator corrugated package, w=180 kgf) up to the specified height. The slip distance between the clamp arm and the target HCP was 0.85 mm. The simulation result of 0.85 mm was 3.7 times lower than the experimental result (3.2 mm) obtained by Park et al. (2017), and it was estimated that the deviation comes from both the experimental error by weight imbalance of target HCP, and excessive simplification during the FE modelling of target HCP.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.41 no.5
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• pp.421-426
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• 2017

In this study, we propose a method for predicting the mechanical properties of the printed circuit board (PCB) that has transversely isotropic characteristics. Unlike the isotropic material, there is no specific test standard for acquisition of the transversely isotropic properties. In addition, common material test methods are not readily applicable to that type of laminated thin plate. Utilizing the natural frequency obtained by a modal test and the sizing optimization technique provided in $OptiStruct^{(R)}$, the mechanical properties of a PCB were derived to minimize the difference between test and analysis results. In addition, the validity of the predicted mechanical properties was confirmed by the MAC (Modal Assurance Criteria) value of each of the compared mode shapes. This proposed approach is expected to be extended to the structural analysis for the design verification of the top product that includes a PCB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.85-94
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• 2003

The asynchronous design methods proved to have the higher performance in power consumption and execution speed than synchronous ones because it just needs to activate the required module without feeding clock in the system. Despite the advantage of CISC machine providing the variable addressing modes and instructions, its execution scheme is hardly suited for a synchronous Pipeline architecture and incurs a lot of overhead. This paper proposes a novel asynchronous pipeline architecture, A80sl, whose instruction set is fully compatible with that of Intel 80C51, an embedded micro controller. We classify the instructions into the group keeping the same execution scheme for the asynchronous pipeline and optimize it eliminating the bubble stage that comes from the overhead of the multi-cycle execution. The new methodologies for branch and various instruction lengths are suggested to minimize the number of states required for instructions execution and to increase its parallelism. The proposed A80C51 architecture is synthesized with 0.35${\mu}{\textrm}{m}$ CMOS standard cell library. The simulation results show higher speed than that of Intel 80C51 with 36 MHz and other asynchronous counterparts by 24 times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.38-48
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• 2006

In this paper, we developed a hardware architecture of Reed-Solomon RS(255,239) decoder for the DMB mobile terminals. The DMB provides multimedia broadcasting service to mobile terminals, hence it should have small dimension for low power and short decoding delay for real-time processing. We modified Euclid algorithm to apply it to the key equation solving which is the most complicated part of the RS decoding. We also designed a small finite field divider to avoid the use of large Inverse-ROM table, and it consumed 17 clocks. After synthesis with Synopsis on Samsung STD130 $0.18{\mu}m$ Standard Cell library, the Euclid block had 30,228 gates and consumed 288 clocks, which gave the 25% reduced area compared to other existing designs. The size of the entire RS decoder was about 45,000 gates.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.66-72
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• 2009

This paper proposes an efficient binary arithmetic encoder for CABAC which is used one of the entropy coding methods for H.264/AVC. The present binary arithmetic encoding algorithm requires huge complexity of operation and data dependency of each step, which is difficult to be operated in fast. Therefore, renormalization exploits 2-stage pipeline architecture for efficient process of operation, which reduces huge complexity of operation and data dependency. Context model updater is implemented by using a simple expression instead of transIdxMPS table and merging transIdxLPS and rangeTabLPS tables, which decreases hardware size. Arithmetic calculator consists of regular mode, bypass mode and termination mode for appearance probability of binary value. It can operate in maximum speed. The proposed binary arithmetic encoder has 7282 gate counts in 0.18um standard cell library. And input symbol per cycle is about 1.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.9
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• pp.1-6
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• 2010

H.264 video coding standard is widely used due to the high compression rate and quality. H.264 decoders usually have pipeline architecture by a macroblock or a $4{\times}4$ sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and the requirement of high data bandwidth and high performance processing units. We propose adaptive pipeline architecture for H.264 decoders for efficient decoding and lower the requirement of the bandwidth for the memory bus. Parameters and coefficients are delivered using hand-shaking communication through dedicated interconnections and frame pixel data are transferred using AMBA AHB network. The processing time of each block is variable depending on the characteristics of images, and the processing units start to work whenever they are ready. An H.264 decoder is designed and implemented using the proposed architecture to verify the operation using an FPGA.