• Title/Summary/Keyword: Korea Design Standard

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A Design of 250-MSamples/s 8-Bit Folding Analog to Digital Converter using Transistor Differential Pair Folding Technique (트랜지스터 차동쌍 폴딩 기법을 적용한 250-MSamples/s 8-비트 폴딩 아날로그-디지털 변환기의 설계)

  • 이돈섭;곽계달
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.11
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    • pp.35-42
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    • 2004
  • A CMOS folding ADC with transistor differential pair folding circuit for low power consumption and high speed operation is presented in this paper. This paper explains the theory of transistor differential pair folding technique and many advantages compared with conventional folding and interpolation circuits. A ADC based on transistor differential pair folding circuit uses 16 fine comparators and 32 interpolation resistors. So it is possible to achieve low power consumption, high speed operation and small chip size. Design technology is based on fully standard 0.25${\mu}{\textrm}{m}$ double poly 2 metal n-well CMOS process. A power consumption is 45mW at 2.5V applied voltage and 250MHz sampling frequency. The INL and DNL are within $\pm$0.15LSB and $\pm$0.15LSB respectively. The SNDR is approximately 50dB at 10MHz input frequency.

THREE DIMENSIONAL FINITE ELEMENT STRESS ANALYSIS OF FIVE DIFFERENT TAPER DESIGN IMPLANT SYSTEMS (3차원 유한요소법적 분석을 이용한 5종의첨형 임플랜트에 발생하는 응력의 비교연구)

  • Byun, Sang-Ki;Park, Won-Hee;Lee, Young-Soo
    • The Journal of Korean Academy of Prosthodontics
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    • v.44 no.5
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    • pp.584-593
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    • 2006
  • Statement of problem : Dental implant which has been developed gradually through many experiments and clinical applications is presently used to various dental prosthetic treatments. To conduct a successful function of implant prosthesis in oral cavity for a long time, it is important that not only structure materials must have the biocompatibility, but also the prosthesis must be designed for the stress, which is occurred in occlusion, to scatter adequately of load support. Therefore, it is essential to give the consideration about the stress analysis of supporting tissues for higher successful rates. Purpose : Recently, many implant manufacturing company produce various taper design of root form implant, the fixture is often selected. However, the stress analysis of taper form fixture still requires more studies. Material and method : This study we make the element models that five implant fixture; Branemark system(Nobel Biocare, Gothenberg, Sweden), Camlog system(Altatec, Germany), Astra system(Astra Tech, Sweden), 3i system(Implant Innovations Inc, USA), Avana system(Osstem, Korea) were placed in the area of mandibular first premolar and prosthesis fabricated, which we compared with stress distribution using the three-dimension finite element analysis under two loading condition. Results : This study compares the aspect of stress distribution of each system with the standard of Von mises stress, among many resulted from finite element analysis so that this research gets the following results. 1. In all implant system, oblique loading of maximum Von mises stress of implant, alveolar bone and crown is higher than vertical loading of those. 2. Regardless of loading conditions and type of system, cortical bone which contacts with implant fixture top area has high stress, and cancellous bone has a little stress. under the vertical loading, maximum Von mises stress is more higher in order of Branemark, Camlog, Astra, 3i, Avana. under the horizontal loading, maximum Von mises is more higher in order of Camlog, Branemark, Astra, 3i, Avana.

Silicon Substrate Coupling Modeling, Analysis, and Substrate Parameter Extraction Method for RF Circuit Design (RF 회로 설계를 위한 실리콘 기판 커플링 모델링, 해석 및 기판 파라미터 추출)

  • Jin, Woo-Jin;Eo, Yung-Seon;Shim, Jong-In
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.12
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    • pp.49-57
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    • 2001
  • In this paper, equivalent circuit model and novel model parameter extraction method of a silicon(Si) substrate are presented. Substrate coupling through Si-substrate is quantitatively investigated by analyzing equivalent circuit with operating frequency and characteristic frequencies (i.e., pole and zero frequency) of a system. For the experimental verification of the equivalent circuit and parameter extraction method, test patterns are designed and fabricated in standard CMOS technology with various isolation distances, substrate resistivity, and guard-ring structures. Then, these are measured in l00MHz-20GHz frequency range by using vector network analyzer. It is shown that the equivalent-circuit-based HSPICE simulation results using extracted parameters have excellent agreement with the experimental results. Thus, the proposed equivalent circuit and parameter extraction methodology can be usefully employed in mixed-signal circuit design and verification of a circuit performance.

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Design of Closed-Form QMF Filters with Maximally Flat and Half-Band Characteristics in the Frequency Domain (주파수 영역에서 최대평탄과 하프대역 특성을 갖는 폐쇄형 QMF 필터들의 설계)

  • Jeon, Joon-Hyeon
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.4 s.316
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    • pp.70-77
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    • 2007
  • Two kinds of QMF(Quadrature Mirror Filter) pairs are used in JPEG2000 standard, which don't have QMF distortions. However, the QMF pairs have the main disadvantages such that there are gentle roll-off rate, ripples in the passband and unequal band decomposition. In this paper, Maxflat(maximally flat) QMF pairs with a half-band gain are proposed for overcoming these problems. Maxflat QMF pairs are realized due to generalized closed-form formulas, and the filters have maximally flat response in the passband/stopband as well as sharp roll-off rate in the transition band. Comparing proposed filters and JPEG2000's filters in frequency domain, it is found that proposed filters have better performance JPEG2000's filters. Moreover, Maxflat QMF pairs show stopband-attenuation exceeding 200 dB almost everywhere.

A Design and Implementation of modified ZigBee using the Directed-Messaging for Energy Efficiency Improvement (에너지 효율성 향상을 위하여 방향성 메시징을 사용하는 수정된 지그비의 설계 및 구현)

  • Khil, A-Ra
    • Journal of the Korea Society of Computer and Information
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    • v.17 no.10
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    • pp.99-105
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    • 2012
  • ZigBee is the low power, low cost and low data rate wireless personal area network(LR-WPAN) standard. The Directed-Messaging is the protocol which improves the energy efficiency through reducing the redundant message transmission by transmitting messages with directional information toward the specified sub-network area in wireless sensor network using broadcasting. In this paper, we design and implement the experimental grid sensor network using ZigBee modified by the Directed-Messaging for the energy efficiency improvement. The experimental sensor network in this paper is configured with Nano24 supporting the ADV message and the routing management module modified to use the directional information. The energy efficiency improvement of the experimental sensor-network by evaluating the experimental results according to transmitting ADV message.

Seismic Performance Evaluation of Special Moment Steel Frames with Torsional Irregularities - I Seismic Design (비틀림 비정형을 갖는 철골특수모멘트골조의 내진성능평가 - I 내진설계)

  • Han, Sang Whan;Kim, Tae O;Ha, Seong Jin
    • Journal of Korean Society of Steel Construction
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    • v.29 no.5
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    • pp.361-368
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    • 2017
  • ASCE 7-10 defines the torsional irregular structure as the one that has large torsional responses caused by the eccentricity. The code requires that these structures should be designed abide by the torsional provisions. This study evaluates the influence of torsional provisions on the performance of the designed multiple steel moment frames with different eccentricity. In this study, 3D response history analyses are performed. The results show that the moment frame design according to the standard with torsional irregularity provisions showed larger performance as the eccentricity increased and the distribution of plastic hinges similarly to orthopedic structures.

Design of a 960MHz CMOS PLL Frequency Synthesizer with Quadrature LC VCO (960MHz Quadrature LC VCO를 이용한 CMOS PLL 주파수 합성기 설계)

  • Kim, Shin-Woong;Kim, Young-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.61-67
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    • 2009
  • This paper reports an Integer-N phase locked loop (PLL) frequency synthesizer which was implemented in a 250nm standard digital CMOS process for a UHF RFID wireless communication system. The main blocks of PLL have been designed including voltage controlled oscillator, phase frequency detector, and charge pump. The LC VCO has been used for a better noise property and low-power design. The source and drain juntions of PMOS transistors are used as the varactor diodes. The ADF4111 of Analog Device has been used for the external pre-scaler and N-divider to divide VCO frequency and a third order RC filter is designed for the loop filter. The measured results show that the RF output power is -13dBm with 50$\Omega$ load, the phase noise is -91.33dBc/Hz at 100KHz offset frequency, and the maximum lock-in time is less than 600us from 930MHz to 970MHz.

Design of Prediction Unit for H.264 decoder (H.264 복호기를 위한 효율적인 예측 연산기 설계)

  • Lee, Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.7
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    • pp.47-52
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    • 2009
  • H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation and management of the reference pixels. The reference pixels read from external memory using efficient memory management for data reuse is necessary along with the high performance interpolators. We propose the architecture of a motion compensation unit for H.264 decoders. It is composed of 2-dimensional circular register files, a motion vector predictor and high performance interpolators with low complexity. The 2-dimensional circular register files reuse reference pixel data as much as possible, and feed reference pixel data to interpolators without any latency and complex logic circuits. We design a motion compensation unit and a intra-prediction unit and integrate them into a prediction unit and verify the operation and the performance.

Program design of the education subject curriculum by the department of emergency medical technology based on National Competency Standards key competencies (NCS 직업기초능력 기반 응급구조(학)과 교양 교과목 편성 연구)

  • Hong, Sung-Gi;Koh, Bong-Yeun;Kim, Soo-Tae
    • The Korean Journal of Emergency Medical Services
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    • v.20 no.3
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    • pp.37-47
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    • 2016
  • Purpose: The purpose of the study was to establish an education curriculum subject program design for the department of emergency medical technology based on National Competency Standards (NCS) key competencies. Methods: A self-reported questionnaire was completed by 180 level 1 emergency medical technicians in K area from June 15 to 20, 2016. Except for 14 incomplete questionnaires, 141 data were analyzed. The study instrument included general characteristics of the subjects (7 items) and importance and satisfaction levels for 10 key competencies including 34 items of subfactors by a Likert 5-point scale using Borich Needs Assessment Model. A locus for focus model (LF model) was used to derive the top priority key competencies for the education curriculum. Data were analyzed by SPSS v. 20.0. Results: The order of education needs of the program included interpersonal competency (1.442), communication competency (1.384), problem solving competency (1.185) and professional ethics competency (1.149). In the LF model, the required jey competencies included interpersonal competency, communication competency, professional ethics competency, and problem solving competency. Conclusion: The study results coincided with standard education curriculum guidelines. Our resluts can provide a valid reference for the department of emergency medical technology.

Analysis of Battery Performance Test for DC Power System in Nuclear Power Plant (원자력발전소 직류전원계통용 축전지 성능시험 분석)

  • Kim, Daesik;Cha, Hanju
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.63 no.2
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    • pp.61-68
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    • 2014
  • Function of battery bank stores energy for DC load in general, and DC power system of the nuclear power plant is used to supply DC loads for safety- featured instrumentation and control such as inverter, class 1E power system control and indication, and station annunciation. Class 1E DC power system must provide a power for the design basis accident conditions, and adequate capacity must be available during loss of AC power and subsequent safe shutdown of the plant. In present, batteries of Class 1E DC power system of the nuclear power plant uses lead-acid batteries. Class 1E batteries of nuclear power plants in Korea are summarized in terms of specification, such as capacity, discharge rate, bank configuration and discharge end voltage, etc. This paper summarizes standards of determining battery size for the nuclear power plant, and analyzes duty cycle for the class 1E DC power system of nuclear power plant. Then, battery cell size is calculated as 2613Ah according to the standard. In addition, this paper analyzes performance test results during past 13 years and shows performance degradation in the battery bank. Performance tests in 2001 and 2005 represent that entire battery cells do not reach the discharge-end voltage. Howeyer, the discharge-end voltage is reached in 14.7% of channel A (17 EA), 13.8% of channel B (16 EA), 5.2% of channel C (6 EA) and 16.4% of channel D (19 EA) at 2011 performance test. Based on the performance test results analysis and size calculation, battery capacity and degradation by age in Korearn nuclear power plant is discussed and would be used for new design.