• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.53-60
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• 2009

A low-power/small-area 128-point FFT processor is designed, which is based on logarithmic number system (LNS) and some design techniques to minimize both hardware complexity and arithmetic error. The complex-number multiplications and additions/subtractions for FFT computation are implemented with LNS adders and look-up table (LUT) rather than using conventional two's complement multipliers and adders. Our design reduces the gate counts by 21% and the memory size by 16% when compared to the conventional two's complement implementation. Also, the estimated power consumption is reduced by about 18%. The LNS-based FFT processor synthesized with 0.35 ${\mu}m$ CMOS standard cell library has 39,910 gates and 2,880 bits memory. It can compute a 128-point FIT in 2.13 ${\mu}s$ with 60 MHz@2.5V, and has the average SQNR of 40.7 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.137-141
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• 2007

This paper proposes a cost-effective architecture design of an angle-of-arrival (AOA) estimator based on the multiple signal identification and classification (MUSIC) algerian in UWB systems adapting Multi-band OFDM (MB-OFDM) techniques with two-receive antennas. In the proposed method, by modifying the equations of algorithm in order to remove the high computational functions, the computation power can be significantly reduced without significant performance degradation. The proposed architecture is designed and verified by Verilog HDL, and implemented into 0.13um CMOS standard cell and Xilinx FPGA circuits for the estimation of hardware complexity and computation power. From the results of the implementations, we can find that the proposed circuits reduces the hardware complexity by about 43% and the estimated computation power by about 23%, respectively, compared to the architecture employing the original MUSIC algorithm.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.29 no.6
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• pp.389-398
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• 2017

The re-analysis on the stable weight of the concrete armor unit (CAU) at the roundhead and the suggestion of the covering range at the roundhead with the increased weight of CAU were conducted. Tetrapods were applied to the tests and the three dimensional hydraulic tests were performed. The test results for the stable weight at the roundhead area were similar to the guides from Korean Design Standard for Harbour and Fishery Port (MOF, 2014) and Coastal Engineering Manual (USACE, 2005). The investigation of covering range at the roundhead of rubble mound structures armoured with Tetrapods was suggested that the length of five times of the design wave height from the tip of the superstructure was needed and appropriate. Both sides of the superstructure should be covered with increasing weighted CAU to satisfy the stability at roundhead area.

• Journal of the Korea Institute of Building Construction
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• v.15 no.6
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• pp.597-605
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• 2015

The method of concrete mix design used in this study aims to achieve the identical specified design strength, applying different types and replacement ratio of mineral admixtures and afterwards, fire tests were conducted using the standard time-temperature curve specified in the ASTM E119 to identify the influences of the types of mineral admixtures on the fire resistance performance of high strength concrete(HSC). The least spalling was observed in the test specimen containing blast furnace slag as a partial replacement of cement, while the most significant spalling phenomena were observed in the blast furnace slag test specimen that silica-fume was added in. In particular, the reasonable volume of spalling was observed when solely replaced by silica fume. However, the influence of the cement replacement by silica fume and blast furnace slag on the increases of spalling can be explained through blocked pores by the fine particles of silica fume, leading to decreases in permeability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.24-33
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• 2006

The effective geometry processing IP architecture for mobile SoC that has real time 3D graphics acceleration performance in mobile information system is proposed. Base on the proposed IP architecture, we design the floating point arithmetic unit needed in geometry process and the floating point geometry processor supporting the 3D graphic international standard OpenGL-ES. The geometry processor is implemented by 160k gate area in a Xilinx-Vertex FPGA and we measure the performance of geometry processor using the actual 3D graphic data at 80MHz frequency environment The experiment result shows 1.5M polygons/sec processing performance. The power consumption is measured to 83.6mW at Hynix 0.25um CMOS@50MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.5 s.305
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• pp.43-50
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• 2005

This paper describes some IC(integrated circuits) design and implementation techniques of low power multi-band Gm-C bandpass filter for body composition analyzer. Proposed BPF(bandpass filter) can be selected from three bands(20 KHz, 50 KHz, 100 KHz) by control signal. To minimize die area, a simple center frequency tuning scheme is used. And to reduce power consumption, operational transconductance amplifier operated in the sub-threshold region is adopted. The proposed BPF is implemented with 0.35 um 2-poly 3-metal standard CMOS technology Chip area is $626.42um\;{\times}\;475.8um$ and power consumption is 700 nW@100 KHz.

• Journal of Families and Better Life
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• v.24 no.5 s.83
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• pp.89-99
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• 2006

The purpose of this study was to devise guidelines for the kitchen workspace of the aged by examining current usage. To achieve this objective, surveys were conducted and measurement were taken between June 15 and lune 30, 2005. The data were gathered from 50 women over 65- years-old who live in the downtown and suburbs of Seoul, Korea. The collected data were processed using SPSS 12.0 for Microsoft Windows and resulted in the following conclusions: The kitchen for the aged needs to be laid out in ㄱ-shape and the refrigerator needs to be positioned prominently. The height of the work counter is relative to the user's height (${\times}0.49{\sim}056$). and the length varies depending on the available space of the house and the type of work counter needed: however it was found that it should be at least 270cm Concerning the depth of the work counter, the standard sizes (60cm) currently on the market did not cause any inconvenience. It was found that the sink must be designed to allow for some space at the bottom so as to ensure comfortable sedentary work. Also, an electrical oven was preferred over a gas-fuelled one. Finally, the height of the upper cabinet should be relative to the user's height at ${\times}0.85{\sim}1.0$ from the floor to the bottom of the cabinet.

• Archives of design research
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• v.17 no.2
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• pp.437-450
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• 2004

Advancement of the media it will be able to express the development and information of computer system causes a problem, how to get the information from plenty of digital data. It needs to the research that provides efficient interface to the user and presents the information visualization standard to the author Consequently, From this paper it investigated analysis of the dynamic diagram and the computer software it led development process of information visualization and result of development outcome. Important developing forms of Information visualization are include Element, Expression, Interface. For developing information visualization model, First, Find the element from many kind of media, include graphic. Second, Find form of the expression from past the diagram which comes to be used plentifully. Last, To get appropriate result it applies the interface, necessary from the interface component which is various uses from computer program. like this, on this paper presents about important three visualization developing forms with detail examples.