• Journal of the Korea Society of Computer and Information
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• v.15 no.4
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• pp.107-118
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• 2010

The user interface is the medium, which provides the users to have an access to the web-based information system. The user interface is the means of improving usability and accessibility for the user, as well as being the core component in the web-based information system. In this paper, the audit framework of the user interface was developed to upgrade the usability and accessibility; it was based on the three basic components of the current audit framework in the web-based information system. At the time of an audit, the UI process of the 'Analysis', 'UI Design', 'UI Production', and 'Test' was defined, which was analyzed through the web development methodology. Also, for the area of an audit, the 'Information', 'Design', and 'Technology' were defined by the analysis of the components that makes up the user interface, From the view of an audit, the standard criteria of an assessment were set as 'Usability', 'Accessibility', and 'Cross Browsing'. Through the framework that was proposed in this paper, practical audit applies the performed examples. By this, the efficiency of the proposed framework was verified.

• Journal of the Korea Society of Computer and Information
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• v.13 no.3
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• pp.45-55
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• 2008

Due to the increasing complexity of embedded system design, automatic code generation of embedded software and hardware-software co-design methodologies are gaining great interest from industries and academia. Such an automatic design methodologies are always demanding a formal system specification languages for defining designer's idea clearly and precisely. In this paper, we propose automatic embedded C code generation from SDL (Specification and Description Language, ITU-T recommended the SDL as a standard system description language) with considering a real-time uC/OS-II operating system. Our automatic embedded C code generator is expected to provide a fast specification, verification and performance evaluation platform for embedded software designs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.47-54
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• 2000

We designed asynchronous event logic library with 0.25um CMOS technology and interface chip for heterogeneous system with high-speed asynchronous FIFO operating at 1.6GHz. Optimized asynchronous standard cell layouts and Verilog models are designed for top-down design methodology. A Method for mitigating a design bottleneck when it comes to tolerate clock skew is described. This communication scheme using clock control circuits, which is used for the free of synchronization failures, is analyzed and implemented. With clock control circuit and FIFO, high-speed communication between synchronous modules operating at different clock frequencies or with asynchronous modules is performed. The core size of implemented high-speed 32bit-interface chip for heterogeneous system is about $1.1mm{\times}1.1mm$.

• Journal of the Korean Institute of Educational Facilities
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• v.22 no.1
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• pp.37-45
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• 2015

Over the years, great attention has been shown to the function of the campus facilities that should be well-equipped, operated and maintained to better support university's two main goals: providing education and supporting research. Properly managing campus facilities is the initial step to be prepared to meet the rapidly changing global educational standard. However, so far, no definitive answer has been given to the question of what service level/scope is appropriate for the effective campus facility management (FM) in Korea. Therefore, at the outset, it is imperative to establish the framework for the standardized campus FM services. The main focus of this research is to provide comprehensive understanding on the campus FM by establishing the framework in the form of FM performance indicator (PI). As the first step, FM standards set by Korean Agency for Technology and Standards (KATS) has been thoroughly reviewed and analyzed to establish the framework for FM standards applicable to campus facility management. Secondly, extensive literature review on the development of performance indicator (PI) for the educational facilities has been conducted to classify PI types and complement FM_KS. Finally, specific guideline and PIs developed by APPA which is globally well-known association in the field of FM for higher education facilities has been added to the combined PI which is the mixed form of FM_KS and PIs from the previous literature. This research provides campus facility managers and FM outsourcing service providers with framework in the form of PI to support future directions of effective campus FM services.

• Journal of the Korea Society of Computer and Information
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• v.19 no.2
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• pp.91-99
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• 2014

This paper is about design and implementation of 'SeaMap' importer module which is for map-based application using 'SeaMap' data. 'SeaMap' data importer is a module that reads 'SeaMap' data in consistent form and offers using easily change the format and the internal data structure in the application. Design of data importer module is based on analyzing characteristic of 'SeaMap'. The comparative analysis between the data type of 'SeaMap' and standard S-57 Electronic Navigation Chart (ENC) of the International Hydrographic Organization (IHO), based on this, to be applicable of S-52 standards 'SeaMap' data is defined as a structure of data. The importer module is designed and converted to allow to use distribution type of 'SeaMap' data sets in map application, parsing 'SeaMap' data around the object defining transformation data structure. In addition, we implemented a 'SeaMap' data viewer in order to test our 'SeaMap' data importer module.

• Journal of Korean Association for Spatial Structures
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• v.9 no.4
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• pp.89-96
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• 2009

Apartment is the most favorite residential type which already occupies more than 50 percent of total number of housing unite in Korea. The interior space design shows various changes of trends within old and legal standard in terms of basic dimension. The most important function of housing means that Provides comfortable living spaces for a family and enjoying relaxation of stress form social activities. This residential space effects direct or indirect to each family members self-satisfaction and relationship. The basic factor for space design brings dimension which is enable space efficiency together with behavioral route, size of electronics and furnitures. Apartment dwelling type was introduced from out of countries. From the very beginning that inharmonious conflicts found and adjusted for several decades. But, the changes of body conditions of new generation has not considered as a dwelling space design yet. This research may call for attention of changing human scale standards for housing in various field of study.

• Convergence Security Journal
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• v.17 no.2
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• pp.15-22
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• 2017

This paper presents new 8-bit implementation of AES. Most typical 8-bit AES designs are to reduce the circuit area by sacrificing its throughput. The presented AES architecture employs two separated S-box to perform round operation and key generation in parallel. From the simulation results of the proposed AES-128, the maximum critical path delay is 13.0ns. It can be operated in 77MHz and the throughput is 15.2 Mbps. Consequently, the throughput of the proposed AES has 1.54 times higher throughput than the other counterpart although the area increasement is limited in 1.17 times. The proposed AES design enables very low-area design without sacrificing its performance. Thereby, it can be suitable for the various IoT applications that need high speed communication.

• Progress in Superconductivity and Cryogenics
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• v.16 no.2
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• pp.29-32
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• 2014

The critical current, $I_c$ of HTS superconducting tapes can be measured by transport or contactless method. Practically, the transport method using the four-probe method is the most common. In this study, a simple test procedure by clipping the voltage lead taps have been introduced instead of soldering which reduces time and effort and thereby achieving a much faster measurement of $I_c$. When using a pair of iron clips, $I_c$ value decreased as compared with the measured one by standard method using soldered voltage taps and varies with the width of the clipped specimen part. However, when using a pure Cu clip, both by clipping and by soldering voltage taps give a comparable result and $I_c$ measured are equal and close to the samples specification. As a result, material to be used as voltage clip should be considered and should not influence the potential voltage between the leads during $I_c$ measurement. Furthermore, the simulation result of magnetic flux during $I_c$ measurement test showed that the decrease of $I_c$ observed in the experiment is due to the magnetic flux density, $B_y$ produced at the clipped part of the sample by the operating current with iron clips attached to the sample.

• Korean Journal of Construction Engineering and Management
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• v.19 no.4
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• pp.82-92
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• 2018

Considering that earlier stage of construction project has a great influence on the possibility of lowering of environmental load, it is important to build and utilize system that can support effective decision making at the initial stage of the project. In this study, we constructed an environmental load estimation model that can be used at the early stage of the project using basic design factors. The model was constructed by using the artificial neural network to estimate environmental load by applying to planning stage (ANN-1), basic design stage (ANN-2). The result of test, shows that average of absolute measuring efficiency and standard deviation of ANN-1 and ANN-2 were 11.19% / 5.30% and 9.59% / 3.09% each. This result indicates that the model using the input variables extended with the project progress has high reliability and it is considered to be effective in decision support at the initial design stage of the project.