• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.7
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• pp.1608-1616
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• 2015

This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.12
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• pp.2333-2340
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• 2016

A LEA (Lightweight Encryption Algorithm) crypto-processor was designed, which supports three master key lengths of 128/ 192/256-bit, ECB and CTR modes of operation. To achieve high throughput rate, the round transformation block was designed with 128 bits datapath and a pipelined structure of 16 stages. Encryption/decryption is carried out through 12/14/16 pipelined stages according to the master key length, and each pipelined stage performs round transformation twice. The key scheduler block was optimized to share hardware resources that are required for encryption, decryption, and three master key lengths. The round keys generated by key scheduler are stored in 32 round key registers, and are repeatedly used in round transformation until master key is updated. The pipelined LEA processor was verified by FPGA implementation, and the estimated performance is about 8.3 Gbps at the maximum clock frequency of 130 MHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.3A
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• pp.399-405
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• 2000

In this paper, we deal with block cipher algorithm IDEA(international data encryption algorithm), previously known as typical block cipher system. first of all, analysing key scheduler we classify the key sequences with the used key bit and the unused key bits in each round. with this properties we propose the two method, which are differential analysis using differences of plaintext pairs and linear analysis using LSB bit of plaintexts and key sequences.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.11
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• pp.33-43
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into a round transformation block, resulting that two consecutive round functions are simultaneously operated. For area-efficient and low-power implementation, the round transformation block is designed to share the hardware resources for encryption and decryption. An efficient on-the-fly key scheduler is devised to supports the three master-key lengths of 128-b/192-b/256-b, and it generates round keys in the first sub-pipeline stage of each round processing. The Verilog-HDL model of the cryptoprocessor was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}m$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.166-168
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• 2014

Coarse-grained reconfigurable architectures (CGRAs) present a potential of high compute throughput with energy efficiency. A CGRA consists of an array of functional units (FU), which communicate with each other through an interconnect network containing transmission nodes and register files. To achieve high performance from the software solutions mapped onto CGRAs, modulo scheduling of loops is generally employed. One of the key challenges in modulo scheduling for CGRAs is to explicitly handle routings of operands from a source to a destination operations through various routing resources. Existing modulo schedulers for CGRAs are slow because finding a valid routing is generally a searching problem over a large space, even with the guidance of well-defined cost metrics. Applications in traditional embedded multimedia domains are regarded relatively tolerant to a slow compile time in exchange of a high quality solution. However, many rapidly growing domains of applications, such as 3D graphics, require a fast compilation. Entrances of CGRAs to these domains have been blocked mainly due to its long compile time. We attack this problem by utilizing patternized routes, for which resources and time slots for a success can be estimated in advance when a source operation is placed. By conservatively reserving predefined resources at predefined time slots, future routings originated from the source operation are guaranteed. Experiments on a real-world 3D graphics benchmark suite show that our scheduler improves the compile time up to 6000 times while achieving average 70% throughputs of the state-of-art CGRA modulo scheduler, edge-centric modulo scheduler (EMS).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.979-985
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• 2012

The design of an efficient scheduler is a key design factor in IEEE 802.16m systems, in order to support services with various QoS smoothly. Although conventional studies of schedules have been suggested, those had problems that are not able to satisfy the delay condition and make the through-put declined, because they only focused on a specific action scenario rather than reflecting practical action scenarios which have real-time and non-real-time traffics variously. In this paper, an efficient uplink scheduling algorithm is proposed for IEEE 802.16m system by introducing the concepts of Virtual Time(VT) and Virtual Finish Time(VFT) based priority determination, and separate buffers for each QoS class in the mobile terminal. Simulation results showed that the proposed scheme had satisfied the delay requirement of real-time services even with improved throughput performance compared to conventional methods.

• Journal of the Korea Society of Computer and Information
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• v.15 no.2
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• pp.1-8
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• 2010

In this paper, we propose a scheduling strategy for grid environment that reduces resource cost. This strategy considers resource cost and job failure rate to efficiently allocate local computing resources. The key idea of our strategy is that we use two-level scheduling using remote and local scheduler. The remote scheduler determines the expected total execution times of jobs using the current network and local system status maintained in its resource database and allocates jobs with minimum total execution time to local systems. The local scheduler recalculates the waiting time and execution time of allocated job and uses it to determine whether the job can be processed within the specified deadline. If it cannot finish in time, the job is migrated other local systems, through simulation, we show that it is more effective to reduce the resource cost than the previous Greedy strategy. We also show that the proposed strategy improves the performance compared to previous Greedy strategy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• Journal of the Korea Computer Industry Society
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• v.2 no.12
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• pp.1557-1562
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• 2001

The echo response time has been a concern in the performance of the UNIX systems, a significant tail always appears in the distribution of echo response time, though the average echo response time is less serious. This paper addresses the issue of echo response times in the UNIX systems. We explain how the Fair Share Scheduler (FSS) works and explain why the FSS might cause excessive echo response times and show by analysis how echo response time reacts to key parameters under FSS. Finally, we present a recommended solution that should improve the echo response time drastically. This solution is a refined FSS which will overcome the echo response time problem while retaining the essence of the FSG. This will enhance the UNIX performance and productivity.