• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.944-947
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• 2002

We implemented a cryptoprocessor with a on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. This scheduler makes the fast generation of the key value and eliminates the memory for software key scheduler. The 128-bit Rijndael processor is implemented based on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps

• 센서학회지
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• 제24권2호
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

• 지능정보연구
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• 제1권1호
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• pp.61-72
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• 1995

Dynamic and explicit ordering of strategies is a key process in modeling knowledge-level problem-solving behavior. This paper addressed the important problem of howl to make the scheduler more knowledge-intensive in a way that facilitates the acquisition, integration, and maintenance of the scheduler control knowledge. The solution a, pp.oach described in this paper involved formulating the scheduler task as a heuristic classification problem, and then implementing it as a classification expert system. By doing this, the wide spectrum of known methods of acquiring, refining, and maintaining the knowledge of a classification expert system are a, pp.icable to the scheduler control knowledge. One important innovation of this research is that of recursive heuristic classification : this paper demonstrates that it is possible to formulate and solve a key subcomponent of heuristic classification as heuristic classification problem. Another key innovation is the creation of a method of dynamic heuristic classification : the classification alternatives that are selected among are dynamically generated in real-time and then evidence is gathered for and aginst these alternatives. In contrast, the normal model of heuristic classification is that of structured selection between a set of preenumerated fixed alternatives.

• 대한임베디드공학회논문지
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• 제7권4호
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• pp.193-199
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• 2012

Virtualization allows multiple commodity operating systems to share on a single physical machine. Resource allocation among virtual machines is a key to determine virtual machine performance. To satisfy time-sensitive task on a domain, hypervisor needs to observe the resource requirements and allocates proper amount of CPU resources in a timely manner. In this paper, we propose a realtime credit scheduler for latency sensitive application on virtual machines. The key idea is to register a time event in the Xen hypervisor. Experiment result shows that the proposed scheme is superior to Credit scheduler.

• 한국산학기술학회논문지
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• 제11권12호
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• pp.4962-4967
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• 2010

스마트 카드는 암호알고리즘의 개발과 더불어 전자상거래 환경이 구축되면서 가치이전의 수단 및 활용분야가 다양하기 때문에 정보 통신망 환경에서 중요한 보안 장치로 수요나 활용면에서 급격한 증가율을 보이고 있다. 따라서 본 논문에서 제안한 스마트 카드용 키 스케쥴러 블록은 다양한 멀티미디어 및 실시간 통신의 암호시스템에 적용할 경우 기존시스템과 호환성이 용이하여 하드웨어 설계와 비도 및 처리속도를 향상시킬 수 있다고 사료된다.

• 융합보안논문지
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• 제15권2호
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• pp.81-89
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• 2015

HIGHT (HIght security and light weighHT) 암호는 기밀성을 요구하는 네트워크 환경에서 사용할 수 있도록 국내에서 개발된 저전력 경량화 64비트 블록 암호 알고리즘이다. 본 논문은 키스케쥴러에 사용되는 LFSR 및 역 LFSR의 4개의 병렬 출력을 허용할 수 있는 구조를 제안하였다. 또한, 각 라운드 연산에 필요한 4개의 서브키를 동일 클럭 사이클에 생성할 수 있도록 구성하였다. 따라서, 전체 HIGHT 암호 프로세서가 단일 시스템 클럭에 의해 제어할 수 있다. VHDL을 이용하여 회로를 합성한 후, 검증한 결과 제안된 키 스케쥴러의 회로 크기는 기존 키 스케쥴러에 비해 9% 감소되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권1호
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• pp.162-166
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• 2017

Earliest virtual deadline zero laxity (EVDZL) algorithm is proposed for mobile GPU schedulers for its improved responsiveness. Responsiveness of user interface (UI) is one of the key factors in evaluating smart devices because of its significant impacts on user experiences. However, conventional GPU schedulers based on completely fair scheduling (CFS) shows a poor responsiveness due to its algorithmic complexity. In this letter, we present the EVDZL scheduler based on the conventional earliest deadline zero laxity (EDZL) algorithm by accommodating the virtual laxity concept into the scheduling. Experimental results show that the EVDZL scheduler improves the response time of the Android UI by 9.6% compared with the traditional CFS scheduler.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 춘계학술대회
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• pp.401-403
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• 2015

128비트 블록암호 알고리듬 LEA(Lightweight Encryption Algorithm)의 효율적인 하드웨어 설계에 대해 기술한다. 저전력, 저면적 구현을 위해 라운드블록과 키 스케줄러의 암호화와 복호화 연산의 하드웨어 자원이 공유되도록 설계하였다. 키 스케줄러 레지스터의 구조를 개선하여 키 스케줄링에 소요되는 클록 사이클 수를 감소시켰으며, 이를 통해 암호화/복호화 성능을 향상시켰다. 설계된 LEA 프로세서는 FPGA 합성결과, 2,364 슬라이스로 구현되었으며, 113 MHz로 동작하여 128/192/256비트 마스터키 길이에 대해 각각 181/162/109 Mbps의 성능을 갖는 것으로 평가되었다.

• 한국콘텐츠학회:학술대회논문집
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• 한국콘텐츠학회 2006년도 추계 종합학술대회 논문집
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• pp.3-6
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• 2006

차세대 웹 서비스로서 Web2.0 이 주목받고 있다. 이러한 웹2.0 서비스를 제공하기 위한 핵심 RIA(Rich Internet Application) 제공 기술로 Ajax(Asynchronous Javascript And XML)기술이 주목 받고 있으며, 이를 기반한 다양한 웹 어플리케이션이 개발 및 서비스 되고있다. 본 논문에서는 Ajax 기반의 웹 어플리케이션 중 스케쥴 관리 프로그램을 살펴보곤 프로젝트 진행시 사용할 수 있는 프로젝트 스케쥴러와 그와 연동되는 프로젝트 로드맵 프로그램을 Ajax 기반의 웹 어플리케이션으로 개발하였다.

• Journal of Astronomy and Space Sciences
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• 제27권4호
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• pp.407-412
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• 2010

Software reusability is one of key factors which impacts cost and schedule on a software development project. It is very crucial also in satellite simulator development since there are many commercial simulator models related to satellite and dynamics. If these models can be used in another simulator platform, great deal of confidence and cost/schedule reduction would be achieved. Simulation model portability (SMP) is maintained by European Space Agency and many models compatible with SMP/simulation model interface (SMI) are available. Korea Aerospace Research Institute (KARI) is developing hardware abstraction layer (HAL) supported satellite simulator to verify on-board software of satellite. From above reasons, KARI wants to port these SMI compatible models to the HAL supported satellite simulator. To port these SMI compatible models to the HAL supported satellite simulator, simulation scheduler is preliminary designed according to the SMI standard.