• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.944-947
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• 2002

We implemented a cryptoprocessor with a on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. This scheduler makes the fast generation of the key value and eliminates the memory for software key scheduler. The 128-bit Rijndael processor is implemented based on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps

• Journal of Sensor Science and Technology
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• v.24 no.2
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• pp.107-112
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

• Journal of Intelligence and Information Systems
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• v.1 no.1
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• pp.61-72
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• 1995

Dynamic and explicit ordering of strategies is a key process in modeling knowledge-level problem-solving behavior. This paper addressed the important problem of howl to make the scheduler more knowledge-intensive in a way that facilitates the acquisition, integration, and maintenance of the scheduler control knowledge. The solution a, pp.oach described in this paper involved formulating the scheduler task as a heuristic classification problem, and then implementing it as a classification expert system. By doing this, the wide spectrum of known methods of acquiring, refining, and maintaining the knowledge of a classification expert system are a, pp.icable to the scheduler control knowledge. One important innovation of this research is that of recursive heuristic classification : this paper demonstrates that it is possible to formulate and solve a key subcomponent of heuristic classification as heuristic classification problem. Another key innovation is the creation of a method of dynamic heuristic classification : the classification alternatives that are selected among are dynamically generated in real-time and then evidence is gathered for and aginst these alternatives. In contrast, the normal model of heuristic classification is that of structured selection between a set of preenumerated fixed alternatives.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.4
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• pp.193-199
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• 2012

Virtualization allows multiple commodity operating systems to share on a single physical machine. Resource allocation among virtual machines is a key to determine virtual machine performance. To satisfy time-sensitive task on a domain, hypervisor needs to observe the resource requirements and allocates proper amount of CPU resources in a timely manner. In this paper, we propose a realtime credit scheduler for latency sensitive application on virtual machines. The key idea is to register a time event in the Xen hypervisor. Experiment result shows that the proposed scheme is superior to Credit scheduler.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.12
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• pp.4962-4967
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• 2010

Security of the electronic commercial transaction especially through the information communication network is gaining its significance due to rapid development of information and communication related fields. For that, some kind of cryptographic algorithm is already in use for the smart card. However, the growing needs of handling multimedia and real time communication bring the smart card into more stringent use of its resources. Therefore, we proposed a key scheduler block of the smart card to facilitate multimedia communication and real time communication.

• Convergence Security Journal
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• v.15 no.2
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• pp.81-89
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• 2015

HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a key scheduler that employs the presented LFSR and reverse LFSR that can generate four outputs simultaneously. In addition, we construct new key scheduler that generates 4 subkey bytes at a clock since each round block requires 4 subkey bytes at a time. Thus, the entire HIGHT processor can be controlled by single system clock with regular control mechanism. We synthesize the HIGHT processor using the VHDL. From the synthesis results, the logic size of the presented key scheduler can be reduced as 9% compared to the counterpart that is employed in the conventional HIGHT processor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.162-166
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• 2017

Earliest virtual deadline zero laxity (EVDZL) algorithm is proposed for mobile GPU schedulers for its improved responsiveness. Responsiveness of user interface (UI) is one of the key factors in evaluating smart devices because of its significant impacts on user experiences. However, conventional GPU schedulers based on completely fair scheduling (CFS) shows a poor responsiveness due to its algorithmic complexity. In this letter, we present the EVDZL scheduler based on the conventional earliest deadline zero laxity (EDZL) algorithm by accommodating the virtual laxity concept into the scheduling. Experimental results show that the EVDZL scheduler improves the response time of the Android UI by 9.6% compared with the traditional CFS scheduler.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.401-403
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• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• Proceedings of the Korea Contents Association Conference
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• 2006.11a
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• pp.3-6
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• 2006

The Web2.0(Next Generation Web Service) is receiving attention by computer industry. Therefore Ajax(Asynchonous Javascript And in), a key RIA(Rich Internet Application) technology of Web 2.0 applications, has also been a matter of interest. And multiple Web applications which are based on Ajax are being developed and delivered. This paper deals with 'Scheduler Applications/Services' of the web application that utilize Ajax. Plus, this paper is aimed at developing, Project Management Scheduler and Project Roadmap, using web applications that utilize Ajax.

• Journal of Astronomy and Space Sciences
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• v.27 no.4
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• pp.407-412
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• 2010

Software reusability is one of key factors which impacts cost and schedule on a software development project. It is very crucial also in satellite simulator development since there are many commercial simulator models related to satellite and dynamics. If these models can be used in another simulator platform, great deal of confidence and cost/schedule reduction would be achieved. Simulation model portability (SMP) is maintained by European Space Agency and many models compatible with SMP/simulation model interface (SMI) are available. Korea Aerospace Research Institute (KARI) is developing hardware abstraction layer (HAL) supported satellite simulator to verify on-board software of satellite. From above reasons, KARI wants to port these SMI compatible models to the HAL supported satellite simulator. To port these SMI compatible models to the HAL supported satellite simulator, simulation scheduler is preliminary designed according to the SMI standard.