• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• Journal of the Korean Society of Industry Convergence
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• v.3 no.2
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• pp.167-178
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• 2000

Software RAID(Redundant Arrays of Inexpensive Disks) is defined as a storage system that provides capabilities of hardware RAID, and guarantees high reliability as well as high performance. In this paper, we propose an enhanced disk scheduling algorithm and a scheme to guarantee reliability of data. We also design and implement software RAID by utilizing these mechanism to develop a storage system for multimedia applications. Because the proposed algorithm improves a defect of traditional GSS algorithm that disk I/O requests arc served in a fixed order, it minimizes buffer consumption and reduces the number of deadline miss through service group exchange. Software RAID also alleviates data copy overhead during disk services by sharing kernel memory. Even though the implemented software RAID uses the parity approach to guarantee reliability of data, it adopts different data allocation scheme. Therefore, we reduce disk accesses in logical XOR operations to compute the new parity data on all write operations. In the performance evaluation experiments, we found that if we apply the proposed schemes to implement the Software RAID, it can be used as a storage system for small-sized video-on-demand servers.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.23 no.6
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• pp.1049-1055
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• 2013

Smartphones are rapidly growing because of easy installation of the apps (application software) that users actually want. There are increasingly many apps that require cryptographic suites to be installed, for instance, for protecting account and financial data. Android platform provides protection mechanisms for memory and storage based on Linux kernel, but they are vulnerable to rooting attacks. In this paper, we analyze security mechanisms of Android platform and point out security problems. We show the security vulnerabilities of several commercial apps and suggest appropriate countermeasures.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.9
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• pp.991-998
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• 2014

Embedded System operates hardware installed like processor, memory device, various input/output devices and software to control them. This thesis presents MPU module and Base board which are efficient industrial control through design and manufacture as developing S5PV210 CPU of SAMSUNG used by ARM Cortex-A8 based on Android which is Open mobile platform is installed to embedded system. Data for temperature and humidity which are received by CAN communication module proved the suitability and validity for the embedded platform design as implementing application program employed the native App with Linux Kernel based on the Android OS and application of HTML5.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1119-1128
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• 2001

본 논문에서는 이차원(2-D) 이산 웨이블릿 면환(Discrete Wavelet Transform, DWT)을 이용한 연상압축기를 FPGA 칩에서 실시간으로 동작 가능하도록 하는 효율적인 메모리 스케줄링 방법(E$^2$M$^2$)을 제안하였다. S/W적으로 위의 메모리 사상 방법을 검증한 후, 실제로 상용화된 SFRAM을 선정하여 메모리 제어기를 구현하였다. 본 논문에서는 Mallet-tree를 이용한 2-D DWT 영상압축 칩을 구현할 경우를 가정하였다. 이 알고리즘은 연산 과정에서 많은 데이터를 정장하여야 하는데, FPGA는 많은 데이터를 저장할 수 있는 메모리가 내장되어 있지 않으므로 외부 메모리를 사용하여야 한다. 외부메모리는 열(row)에 대해서만 연속(burst) 읽기, 쓰기 동작이 가능하기 때문에 Mallet-tree 알고리즘의 데이터 입출력을 그대로 적용할 경우 실시간 동작을 수행하는 DWT 압축 칩을 구현할 수 없다. 본 논문에서는 데이터 쓰기를 수행할 경우에는 메모리 셀(cell)의 수직 방향을 저장시키고 읽기를 수행할 때는 수평으로 데이터의 연속 읽기를 수행함으로써 필터가 항상 수평 방향에 위치하게 하는 방법을 제안하였다. 입방법을 C-언어로 DWT 커넬(Kernel)과 메모리의 에뮬레이터(emulator)를 구현하여 실험한 결과, Mallat-tree 이론을 그대로 적용시켰을 때와 동일한 필터링을 수행할 수 있음을 검증하였다. 또한, 상용화된 SDRAM의 메모리 제어기를 H/W로 구현하여 시뮬레이션 함으로써 본 논문에서 제안한 방법이 실제적인 하드웨어로 실시간 동작을 할 수 있음을 보였다.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.3
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• pp.238-244
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• 2008

Dynamic neural networks have been applied to diverse fields requiring temporal signal processing. This paper presents gamma neural network(GAM) to improve the dynamics of multilayer network. The GAM network uses the gamma memory kernel in the hidden layer of feedforword multilayer network. The GAM network is evaluated in linear and nonlinear system identification, and compared with feedforword(FNN) and recurrent neural networks(RNN) for the relative comparison of its performance. Experimental results show that the GAM network performs better with respect to the convergence and accuracy, indicating that it can be a more effective network than conventional multilayer networks in system identification.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.901-906
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• 2006

In this paper, we describe the implementation of the digital photo frame system that displays the images coming through the memory card of a digital camera. Each image can be recorded with voice in this system, and a function of the mp3 player is implemented as well. We use Intel PXA255 to control the system and modify the bootloader and linux kernel. Also we adapt device driver for this system. For the realization of image display, voice recording and mp3 playing in the basis of the linux system, we program some of the Microwindows system configuration files and program applications here. This study will be a good example to access the development of the digital photo frame based on the linux system using less-power and high performed embedded processor.

• Journal of Information Processing Systems
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• v.4 no.4
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• pp.133-144
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• 2008

Clusters have become a popular alternative for building high-performance parallel computing systems. Today's high-performance system area network (SAN) protocols such as VIA and IBA significantly reduce user-to-user communication latency by implementing protocol stacks outside of operating system kernel. However, emerging parallel applications require a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) make up a large portion of overall communication latency, the reduction of data transfer time is crucial for achieving low-latency communication. In this paper, Eager Data Transfer (EDT) mechanism is proposed to reduce the time for data transfers between the host and network interface. The EDT employs cache coherence interface hardware to directly transfer data between the host and NI. An EDT-based network interface was modeled and simulated on the Linux-based, complete system simulation environment, Linux/SimOS. Our simulation results show that the EDT approach significantly reduces the data transfer time compared to DMA-based approaches. The EDTbased NI attains 17% to 38% reduction in user-to-user message time compared to the cache-coherent DMA-based NIs for a range of message sizes (64 bytes${\sim}$4 Kbytes) in a SAN environment.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.129-138
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• 2018

As recent applications are requiring more CPUs for their performance, manycore systems have evolved. Since existing operating systems do not provide performance scalability in manycore systems, Azalea, a multi-kernel based system, has been developed for supporting performance scalability. Unikernel is a new operating system technology starting with the concept of a library OS. Applying unikernel to Azalea enables an improvement in performance. In this paper, we first analyze the current technology trends of unikernel, and then discuss the applications and effects of unikernel to Azalea. Azalea-unikernel was built in a single image consisting of libOS, runtime libraries, and an application, and executed with the desired number of cores and memory size in bare-metal. In particular, it supports source and binary compatibility such that existing linux binaries can be rebuilt and executed in Azalea-unikernel, and already built binaries can be run immediately without modification with a better performance. It not only achieves a performance enhancement, it is also a more secure OS for manycore systems.

• Journal of Information Processing Systems
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• v.16 no.6
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• pp.1359-1371
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• 2020

In transmitting and receiving such a large amount of data, reliable data communication is crucial for normal operation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumed that an error correction code (ECC) that can detect and correct errors by itself is used in an environment where massive data is sequentially received. Because an embedded system has limited resources, such as a low-performance processor or a small memory, it requires efficient operation of applications. In this paper, we propose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into the embedded system when receiving a large amount of data. In the matrix-vector multiplication that forms the Hamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row (CSR) format, and a sparse matrix-vector product is used. The multiplication operation is performed in the kernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can be performed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board, NVIDIA Jetson TX2, and compared with execution time of the CPU.