• Journal of Integrative Natural Science
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• v.3 no.3
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• pp.153-156
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• 2010

Oxidation behaviors of porous silicon were investigated by the measurement of area of $SiO_2$ vibrational peaks in FT-IR spectra during thermal oxidation of porous silicon at corresponding temperatures. Visible photoluminescent porous silicon samples were obtained from an electrochemical etch of n-type silicon of resistivity between 1-10 ${\Omega}/cm$. The etching solution was prepared by adding an equal volume of pure ethanol to an aqueous solution of HF. The porous silicon was illuminated with a 300 W tungsten lamp for the duration of etch. Etching was carried out as a two-electrode galvanostatic procedure at applied current density of 200 $mA/cm^2$ for 5 min. The porosity of samples prepared was about 80%. After formation of porous silicon, the samples were thermally oxidized at $100^{\circ}C$, $200^{\circ}C$, $300^{\circ}C$, and $400^{\circ}C$, respectively. The growth rate of $SiO_2$ layer of porous silicon was investigated by using FT-IR spectroscopy. The effect of oxidation of porous silicon was presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.83-83
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• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.4
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• pp.261-268
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• 1999

Laser-induced thermochemical etching has been recognized as a new powerful method for processing a variety of materials, including metals, semiconductors, ceramics, insulators and polymers. This study presents characteristics of direct etching for Si substrate using focused argon ion laser beam in aqueous KOH and $CCl_2F_2$ gas. In order to determine process conditions, we first theoretically investigated the temperature characteristics induced by a CW laser beam with a gaussian intensity distribution on a silicon surface. Major process parameters are laser beam power, beam scan speed and reaction material. We have achieved a very high etch rate up to $434.7\mum/sec$ and a high aspect ratio of about 6. Potential applications of this laser beam etching include prototyping of micro-structures of MEMS(micro electro mechanical systems), repair of devices, and isolation of opto-electric devices.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.425-427
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• 1996

New fabrication technique was developed to make three dimensional silicon microstructure with five fold vertical steps through entire wafer thickness. Each step is pre-defined on multiply stacked thermal oxide and silicon nitride (O/N) layers by photolithographies. Multi-stepped silicon microstructure is formed by anisotropic etch in aqueous KOH solution with the patterned nitride film as masking layer. Fabricated microstructure consists of four $16{\mu}m$ thick flexural spring beams, $290{\mu}m$ thick proof mass, mesas for overrange stop with $10{\mu}m$ height from the surface of the proof mass, and the other mesas and V grooves used for assembling this structure to the packaging frame of pendulous servo accelerometer. Using the numerical finite element method (FEM) simulator: ABAQUS, mechanical characteristics of the fabricated microstructure by the developed technique was compared with those of the same structure processed by one step silicon bulk etch followed by oxidation and patterning the etched region.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.241-241
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• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• Transactions of Materials Processing
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• v.13 no.4
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.78-78
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• 2007

In semiconductor devices, Cu has been used for the formation of multilevel metal interconnects by the damascene technique. Also lower dielectric constant materials is needed for the below 65 nm technology node. However, the low-k materials has porous structure and they can be easily damaged by high down pressure during conventional CMP. Also, Cu surface are vulnerable to have surface scratches by abrasive particles in CMP slurry. In order to overcome these technical difficulties in CMP, electro-chemical mechanical planarization (ECMP) has been introduced. ECMP uses abrasive free electrolyte, soft pad and low down-force. Especially, electrolyte is an important process factor in ECMP. The purpose of this study was to characterize KOH and $KNO_3$ based electrolytes on electro-chemical mechanical. planarization. Also, the effect of additives such as an organic acid and oxidizer on ECMP behavior was investigated. The removal rate and static etch rate were measured to evaluate the effect of electro chemical reaction.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.844-847
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• 2001

The application of laser direct etching has been discussed, and believed that the process is a very powerful method for micro machining. This study is focused on the micro patterning technology using laser direct etching process with no chemical damage of the material surface. A new introduced concept of energy synergy effect for surface micro machining is the combination of chemically ion reaction and laser thermal process. The etchant can't etch the material in room temperature, and used Ar laser has not power enough to machine. But, the machining is occurred in local area of the material by the combined energy. Using this process, the material is especially prevented from chemical damage for electric property. We have tested this new concept, and achieved a line with $1{mu}m$ width. The Ar laser with 488nm wavelength was used. The material was Si(100) wafer, and etchant is KOH solution. The application and flexibility of this process is in great hopes for MEMS structures and fabrication of the micro electric device parts.

• 제어로봇시스템학회:학술대회논문집
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• 1995.10a
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• pp.252-258
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• 1995

The purpose of this study is to provide the integrated process control system, utilizing neural network modeling, to search for the appropriate choice input, and to keep the process output within the desired rang in the real etch process.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.4
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• pp.168-171
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• 2003

$YMnO_{3}$ single crystals have been grown by a floating zone technique and the optimal growth conditions were investigated. Their crystallinity and microstructure were characterized by the chemical etch pit patterns, their distribution and the compositional difference depending on the G value. In particular, the microstructural feature was interpreted in terms of compositional deviation along radial direction on (1010) growth plane.