• Korean Journal of Metals and Materials
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• v.47 no.11
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• pp.748-753
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• 2009

The surface morphology and the surface roughness of n-type SiC induced by wet-treatment using 45% KOH and buffered oxide etchant (BOE-1HF : $6H_2O$) were investigated by atomic force microscopy (AFM). While Si-face of SiC could be etched by alkali solutions such as KOH, acidic solutions such as BOE were hardly able to etch SiC. When the rough SiC samples were used, the surface roughness of etched sample was decreased after wet-treatment regardless of etchant, due to the planarization the of surface by widening of scratches formed by mechanical polishing. It was observed that the initial etching was affected by the energetically unstable sites, such as dangling bond and steps. However, when a relatively smooth sample was used, the surface roughness was rapidly increased after treatment at $180^{\circ}C$ for 1 hr and at room temperature for 4 hr by using KOH solution, resulting from the nano-sized structures such as pores and bumps. This indicates that porous SiC surface can be achieved by using purely chemical treatment.

• Electrical & Electronic Materials
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• v.10 no.5
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• pp.481-486
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• 1997

This paper describes the anisotropic etching characteristics of Si in acqueous TMAH/IPA solutions. The etch rates of (100) oriented Si crystal planes decrease with increasing TMAH concentration and IPA concentration. Etchant concentration and etch temperature have a large effect on hillock density. Hillock density strongly increase with lower TMAH concentration and higher etch temperature. The etched (100) planes are covered by pyramidal-shaped hillocks below TMAH 15 wt.%, but very smooth surface is obtained TMAH 25 wt.%. The addition of IPA to TMAH solution leads to smoother surfaces of sidewalls etched planes. Undercutting ratio of pure TMAH solution is much higher than KOH. But, addition of IPA to TMAh the underrcutting ratio reduces by a factor of 3∼4. Therefore, acqueous TMAH/IPA solution is able to use as anisotropic etchant of Si because of full compability with IC fabrication process.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.1
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• pp.1-5
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• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.351-354
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• 2004

This work presents a simple and cost-effective approach for maskless fabrication of positive-tone silicon master for the replica molding of hyperfine elastomeric channel. Positive-tone silicon masters were fabricated by a maskless fabrication technique using the combination of nanoscratch by Nanoindenter ⓡ XP and XOH wet etching. Grooves were machined on a silicon surface coated with native oxide by ductile-regime nanoscratch, and they were etched in a 20 wt％ KOH solution. After the KOH etching process, positive-tone structures resulted because of the etch-mask effect of the amorphous oxide layer generated by nanoscratch. The size and shape of the positive-tone structures were controlled by varying the etching time (5, 15, 18, 20, 25, 30 min) and the normal loads (1, 5 mN) during nanoscratch. Moreover, the effects of the Berkovich tip alignment (0, 45$^{\circ}$) on the deformation behavior and etching characteristic of silicon material were investigated.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.48.1-48.1
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• 2010

Mono-crystalline silicon solar cell is fabricated by using alkali metals. These alkali metal, used in wet etching process, must be removed for the high efficiency solar cell. As wet etching process has been adapted due to its low cost. But lots of alkali metals like potassium remains on the silicon surface and acts as impurities. To remove these alkali metals many of cleaning process have to be applied when solar cell manufacturing process. In terms of alkali metal removal, modified etchant solution is required for concise cleaning process. In this paper ethylenediamine was used and proposed for the substituion of postassium hydroxide.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.5 no.2
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• pp.87-93
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• 1995

Strontium titanate single crystal was grown by floating wne method. Growth conditions are as follows; at air atmosphere, rotation rate of upper and lower shafts were 20 - 25 rpm, 15 - 20 rpm respectively and growth rate was 3 mmlhr. As grown crystal was light brown color and transparent. After annealing, color was faded away. Growth direction was [112] direction and it was confirmed that grown crystal has $SrTiO_3$single phase and stoichiometric composition by XRD and EDS. Etch pit pattern was investigated after chemical etching in $350^{\circ}C$, KOH solution for 5 min and dielectric constant was measured at the range of room temperature ~ $350^{\circ}C$ .

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.156-161
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• 2011

The present study introduces a novel wet etching technique for nanostructure fabrications which usually requires low surface roughness. Using the current method, acquired profiles were smooth even in the nanoscale, which cannot be easily achieved with conventional wet or dry etching methods. As one of the most popular single crystal silicon etchant, potassium hydroxide (KOH) solution was used as a base solvent and two additives, antimony trioxide (Sb2O3) and ethyl alcohol were employed in. Four experimental parameters, concentrations of KOH, Sb2O3, and ethyl alcohol and temperature were optimized at 60 wt.%, 0.003 wt.%, 10 v/v%, and $23^{\circ}C$, respectively. Effects of additives in KOH solution were investigated on the profiles in both (110) and (111) planes of single crystal silicon wafer. The preliminary results show that additives play a critical role to decrease etch rate significantly down to ~2 nm/min resulting in smooth side wall profiles on (111) plane and enhanced surface roughness.

• Korean Journal of Metals and Materials
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• v.46 no.4
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• pp.217-222
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• 2008

Characteristics of etching and induced surface morphology variation by wet-etching of n-face n-type GaN were investigated using KOH solutions. It was observed that hexagonal pyramids were formed on the etched surface regardless of etching conditions. However, the size of the hexagonal pyramids was changed as the etching time and temperature increased, respectively. Initially, as the etching time and concentration of KOH solution increased, the hexagonal pyramid was observed to be dissociated into smaller pyramids. However, as the etching time increased further, the size of the hexagonal pyramids increased again, indicating that the etching of N-face n-type GaN by KOH solutions proceeded through the evolution of hexagonal pyramids, such as formation, dissociation and enlargement of pyramids. Furthermore, it was also observed that there is a correlation between the photoluminescence intensity of the etched surface and the value of root-mean-square roughness. The intensity of PL increased as the roughness value increased due to the enhancement of the extraction efficiency of the generated photons.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.79-79
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• 1999

The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.47.2-47.2
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• 2010

For reducing outer reflection in mono-crystalline silicon solar cell, wet texturing process has been adapted for long period of time. Nowadays mixed solution with potassium hydroxide and isopropyl alcohol is used in silicon surface texturing by most manufacturers. In the process of silicon texturing, etch rate is very critical for effective texturing. Several parameters influence the result of texturing. Most of all, temperature, process time and concentration of potassium hydroxide can be classified as important factors. In this paper, temperature, process time and concentration of potassium hydroxide were set as major parameters and 3-level test matrix was created by using robust design for the optimized condition. The process optimization in terms of lowest reflection and stable etch rate can be traced by using robust design method.