• Journal of the Korea Society of Computer and Information
• /
• v.18 no.10
• /
• pp.1-12
• /
• 2013

This paper explores design space of many-core processors for a fire feature extraction algorithm. This paper evaluates the impact of varying the number of cores and memory sizes for the many-core processor and identifies an optimal many-core processor in terms of performance, energy efficiency, and area efficiency. In this study, we utilized 90 samples with dimensions of $256{\times}256$ (60 samples containing fire and 30 samples containing non-fire) for experiments. Experimental results using six different many-core architectures (PEs=16, 64, 256, 1,024, 4,096, and 16,384) and the feature extraction algorithm of fire indicate that the highest area efficiency and energy efficiency are achieved at PEs=1,024 and 4,096, respectively, for all fire/non-fire containing movies. In addition, all the six many-core processors satisfy the real-time requirement of 30 frames-per-second (30 fps) for the algorithm.

• Proceedings of the Korea Contents Association Conference
• /
• 2009.05a
• /
• pp.17-22
• /
• 2009

DaVinci processors are popular media processors for implementing embedded multimedia applications. They support dual core architecture: ARM9 core for video I/O handling as well as system management and peripheral handling, and DSP C64+ core for effective digital signal processing. In this paper, we propose our efforts for optimal implementation of object tracking algorithm in DaVinci-based smart camera which is being designed and implemented by our laboratory. The smart camera in this paper is supposed to support object detection, object tracking, object classification and detection of intrusion into surveillance regions and sending the detection event to remote clients using IP protocol. Object tracking algorithm is computationally expensive since it needs to process several procedures such as foreground mask extraction, foreground mask correction, connected component labeling, blob region calculation, object prediction, and etc. which require large amount of computation times. Thus, if it is not implemented optimally in Davinci-based processors, one cannot expect real-time performance of the smart camera.

• Journal of KIISE
• /
• v.43 no.7
• /
• pp.736-743
• /
• 2016

Several studies have reported the impact of core affinity on the network I/O performance of multi-core systems. As the network bandwidth increases significantly, it becomes more important to determine the effective core affinity. Although a framework for dynamic core affinity that considers both network and disk I/O has been suggested, the multiple queues provided by high-speed I/O devices are not properly supported. In this paper, we extend the existing framework of dynamic core affinity to efficiently support the multiple queues of high-speed I/O devices, such as 40 Gigabit Ethernet and NVM Express. Our experimental results show that the extended framework can improve the HDFS file upload throughput by up to 32%, and can provide improved scalability in terms of the number of cores. In addition, we analyze the impact of the assignment policy of multiple I/O queues across a number of cores.

• The Journal of the Korea Contents Association
• /
• v.22 no.6
• /
• pp.24-34
• /
• 2022

Viewing religion as contents, we analyzed the network structure by creating networks on 13 world religions. The whole network was constructed by combining 13 religions, and it showed the characteristics of a scale-free network as a general social network. The world religion network had a very small value of clustering coefficient, unlike the general social network. This seems to be the result of the diversity of terms that describe religion. The core network was constructed by applying K-core algorithm used to create the core network to the whole network. When k-3 was applied, it was too complicated but when k-4 was applied, it was too simple to obtain meaningful results. It indicates that it difficult to apply the K-core algorithm to a network containing a low clustering coefficient. Therefore, core networks were constructed according to the number of key words centered on the hub node to analyze the characteristics of world religions. In addition, meaningful information was derived by constructing the world's five major religious networks and East Asian religious networks. In this study, various information was obtained by analyzing world religions as contents. It was also presented a method of creating and analyzing a core network based on key words for networks with a low clustering coefficient.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2005.11a
• /
• pp.357-360
• /
• 2005

유전자 알고리즘(Genetic Algorithm, GA)은 자연적 진화과정에서 생존 경쟁 측면의 가장 적합한 메커니즘이다. GA를 소프트웨어로 수행하는데 큰 지연시간은 필수적이기 때문에 하드웨어 설계를 이용하여 알고리즘 실행 속도를 증가시키기 위한 많은 연구가 진행되어 왔다. 본 논문에서는 염색체의 임의의 유전인자를 기준으로 입력 받은 염색체에 대하여 GA 연산을 수행하는 유전 연산자를 설계한다. 설계된 디자인을 ARM 코어와 PLD로 구성된 Altera사의 Excalibur칩에 구현하여 동작을 검증하였다.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.1
• /
• pp.135-140
• /
• 2020

Recently, due to the rapid diffusion of intelligent systems and IoT technologies, power saving techniques in real-time embedded systems has become important. In this paper, we propose P-GA (Parallel Genetic Algorithm), a scheduling algorithm aims at reducing the power consumption of real-time systems in multi-core hybrid memory environments. P-GA improves the Proportional-Fairness (PF) algorithm devised for multi-core environments by combining the dynamic voltage/frequency scaling of the processor with the nonvolatile memory technologies. Specifically, P-GA applies genetic algorithms for optimizing the voltage and frequency modes of processors and the memory types, thereby minimizing the power consumptions of the task set. Simulation experiments show that the power consumption of P-GA is reduced by 2.85 times compared to the conventional schemes.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.20 no.4
• /
• pp.135-141
• /
• 2020

Today, CPUs in general-purpose computers such as servers, desktops and laptops, as well as home appliances and embedded systems, consist mostly of multicore processors. In order to improve performance, it is required to use an out-of-order execution processor by Tomasulo algorithm as each core processor. An out-of-order execution processor with Tomasulo algorithm can execute the available instructions in any order and perform speculation in order to reduce control dependencies. Therefore, the performance of an out-of-order execution processor can be significantly improved compared to an in-order execution processor. In this paper, an out-of-order execution processor using Tomasulo algorithm and ARM instruction set is designed using VHDL record data types and simulated by GHDL. As a result, it is possible to successfully perform operations on programs written in ARM instructions.

• The Journal of Society for e-Business Studies
• /
• v.23 no.3
• /
• pp.225-237
• /
• 2018

The demand for processing large data streams is growing rapidly as the generation and processing of large volumes of data become more popular. A variety of large data processing technologies are being developed to suit the increasing demand. One of the technologies that researchers have particularly observed is the data stream clustering with sliding windows. Data stream clustering with sliding windows may create a new set of clusters whenever the window moves. Previous data stream clustering techniques with sliding windows exploit the coresets, also known as group features that summarize the data. In this paper, we present some reformable elements of a group-feature based algorithm, and propose our algorithm that modified the clustering algorithm of the original one. We conduct a performance comparison between two algorithms by using different parameter values. Finally, we provide some guideline for the selective use of those algorithms with regard to the parameter values and their impacts on the performance.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06a
• /
• pp.403-405
• /
• 2012

접미사 트리는 문자열 압축, 텍스트 처리, 생물정보학 등 다양한 응용 분야에서 사용되는 인덱스 자료구조이다. 최근 64bit 하드웨어와 멀티코어 CPU가 보급됨에 따라 메모리상에서 병렬로 접미사 트리를 생성하는 알고리즘이 활발히 연구되고 있다. 본 논문에서는 McCreight의 선형시간 알고리즘과 Chen의 병렬 알고리즘을 기반으로 메모리상에서 접미사 트리를 병렬로 생성하는 구현 방법을 보였으며, TBB, Cilk Plus와 같은 병렬 프로그래밍 라이브러리를 이용하여 병렬 알고리즘을 구현하였다. 알고리즘 실험 결과 병렬로 수행한 알고리즘이 직렬로 수행한 결과보다 최대 4배 가량 성능 향상을 얻을 수 있었으며, 병렬 라이브러리를 사용함으로써 가지는 오버헤드는 극히 적은 것으로 나타났다.

• Journal of Digital Contents Society
• /
• v.19 no.6
• /
• pp.1219-1224
• /
• 2018

Nowaday, smart mobile devices on Internet of Things are required to process and deliver greate amount of data in real-time. Therefore, heterogeneous mult-core architecture such the big.LITTLE core architecture, which shows high energy conservation while guaranteeing high performance, are widely employed on up to date smart mobile devices. The LITTLE cores should be highly utilized to gain higher energy conservation because LITTLE cores have much higher energy efficiency than big cores. In this paper, we propose a core selection algorithm, which tries to firstly assign a real-time task on a LITTLE core rather a big core while the task can be finished within its own deadline. We also perform simulation as performance evaluation to show that our proposed algorithm shows higher energy conservation while guaranteeing the required performance.