• Aerospace Engineering and Technology
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• v.12 no.2
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• pp.1-6
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• 2013

A LEO satellite transmits recorded images to a ground station using an X-band antenna during contact. The X-band antenna points to the ground station according to a TPF (tracking parameter file) during communication time. A TPF generation software generates azimuth and elevation profile which make the antenna point to the ground station using satellite orbit and attitude information and mission information including recording and downlink operation. When the satellite passes above the ground station, azimuth velocity increases rapidly so that jitter may occur if the azimuth velocity is in specific range. In case of realtime mission in which the satellite perform recording and downlink simultaneously, azimuth velocity must be lower than specific value to prevent image blur due to jitter effect. The method to point one virtual ground station has limitation of azimuth velocity reduction. In this paper, we propose the azimuth fixing method to reduce azimuth velocity of X-band antenna. The experimental results show that azimuth velocity of the X-band antenna is remarkably reduced using proposed method.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2006.05a
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• pp.376-379
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• 2006

Reaction Wheel Assembly (RWA) is one of the major disturbance sources that have influence upon the Line of Sight (LOS) of payload. A micro-vibration induced by RWA is propagated through the satellite structure and decrease the LOS stability performance of payload. This effect shall be analyzed through the jitter analysis. If a requirement or specification of payload jitter level is found to be not satisfied according to the jitter analysis campaign, some modification or redesign should be done on the satellite structure or a couple of isolator should be attached on the RWA interface in order to reduce the transmitted vibration level of RWA. The purpose of ???RWA isolator test? is to roughly evaluate the performance of vibration suppression level with a passive RWA isolator made of rubber. For this test, actual RWA is used as a vibration source and a couple of cube-shaped rubber mount designed for satellite is used as a passive isolator. There may be several considerations in order to accommodate RWA isolator to spacecraft such as not only vibration reduction performance but also thermal conduction problem, mechanical size, RWA alignment problem, etc. But in this report the feasibility of RWA isolator is analyzed only in a vibration suppression point of view. As a result, high frequency vibration of RWA above 50Hz is perfectly attenuated with isolators, however, first harmonic components below 50Hz became larger due to the additional low frequency resonance modes of roll, pitch, yaw rigid body motion of RWA+bracket.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.1-7
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• 2007

This paper proposes CMOS semi-digital data recovery with 2X converse oversampling to reduce power consumption and chid area of high definition multimedia interface (HDMI) receivers. Proposed recovery can reduce its power and the effective area by using nt converse oversampling algorithm and semi-digital architecture. Proposed circuit is fabricated using 0.18um CMOS process and measured results demonstrated the power consumption of 14.4mW, the effective area of $0.152mm^2$ and the jitter tolerance of 0.7UIpp with 1.8V supply voltage.)

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.1
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• pp.11-19
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit which becomes more serious problem due to the thin gate oxide and small threshold voltage in nanometer CMOS technology and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9V power supply voltage. The simulation results show that the proposed PLL achieves a 88% jitter reduction at 440MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of $40M{\sim}725MHz$ with a multiplication range of 11023, and the RMS and peak-to-peak jitter are 5ps and 42.7ps, respectively.

• Journal of IKEEE
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• v.13 no.2
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• pp.118-125
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• 2009

With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.490-492
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• 2010

A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about $50{\Omega}$, was implemented using a 70nm 1-poly 3-metal DRAM process with a 1.5V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6A
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• pp.465-473
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• 2005

In this paper, the reduction scheme of Interchannel Interference(ICI) caused by the phase noise in Orthogonal Frequency Division Multiplexing(OFDM) systems for archiving high data rates is proposed. The performance of conventional common phase error(CPE) compensation method is degraded by the phase noise with wide 3dB bandwidth in OFDM systems width a higher-order constellation. After estimating dominant ICI coefficients using pilot subcarriers and data subcarriers adjacent to pilot subcarriers, the proposed scheme compensates OFDM signals distorted by the phase noise using estimated coefficients in the time or frequency domain. Also, in order to determine the length of dominant ICI coefficients effectively, the estimation method of the 3dB bandwidth of the phase noise is proposed. The proposed phase noise reduction method is shown to improve the Bit Error Ratio(BER) performance compared with the conventional CPE compensation.

• Korean Journal of Cognitive Science
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• v.10 no.3
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• pp.29-37
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• 1999

Murakami and Cavanagh (1998a,b, 1999) reported a jitter aftereffect in a static random noise after a period of adaptation to a patch of dynamic random noise. To a account for this phenomenon. they proposed the retinal slip caused by a small eye movements in the unadapted area, which is usually compensated by the visual system to stabilize images but is unsuppressed due to the adaptation. We tested this hypothesis with new experimental method and stimuli that were supposed to nullify or reduce the effect. However. the aftereffect was still observed even under these stimuls conditions More importantly, the perceived aftereffect was rather different from Murakami and Cavanagh's. After adaptation to a counterphase flickering cosine grating, the adjacent unadapted region seems to move away from the observer during the test period instead of jittering in the frontoparallel plane. We proposed a possible explanation for this new phenomenon noting the severe contrast reduction of the adapted region during flickering period. The aftereffect might be due to the flicker-inducing contrast reduction during adaptation that produces different depth planes for the adapted and unadapted region and its restoration during the test period.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2176-2182
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• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.