• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.1-11
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• 2006

With the improvement of information telecommunication technology, the various service in broadband integrated services digital networks have a wide range of delay, delay jitter and cell loss probability requirements according to traffic specification. Therefore, the design of appropriate control schemes that can satisfy the cell loss, delay requirements with various traffic specification for B-ISDN is an extremely important challenging problem. In this paper, we propose a priority control scheme using a window counter and a cell counter per each type of class. In the proposed priority control scheme, for satisfying required service quality, we performed the priority control scheme using the delay/loss factors obtained by comparing window counter with cell counter. The performance of proposed control scheme is estimated by computer simulation. In the results of simulation, we verified that the proposed method satisfied per class requirements as the results showed that cell loss probability has a order of video, data, voice and delay time has a order of video, voice and data.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.1
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• pp.139-150
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• 1997

For high-speed networks, a new ring protocal is proposed in this paper. A ring network combined with destination removal can achieve much higher network throughput than the channel transmission rate. However, such a network exhibits fairness problems. Over a past few years, global fairness algorithms such as ATMR and Metaring have been proposed to solve such problems. But the ring access time delay and fairness in such networks are sensitive to the network parameters such as network size and traffic distribution. In addition to guaranteeing fair ring access to all nodes, there are several other important performance aspects in such networks. The one is that fairness is enforced while node throughputs are kept as high as possible. And another performance measure is access delay and more specifically Head-Of-Line(HOL) delay, i.e., the amount of time the first cell in the transmission buffer of a node has to wait before it accesses the ring. HOL delay is a mijor component in the transmission jitter of the synchronous traffic transmission. A key idea of the proposed ring protocol is to find the nodes that have much more chances to access the ring than any other nodes in the independently distributed node architecture. Since destined by many cells need to share a part of the bandwidths with the next node for the fairness in as much as performance degradation does not become critical. To investigate the performance behavior of the proposed ring protocol for various network condition,s several performance parameters wuch as ring access time delay, and throughput are compared with those of the ATMR and Metaring protocols using simulation package, SIMAN.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.10 no.4
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• pp.71-77
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• 2011

In this paper, we propose a conversational quality measurement (CQM) system for providing the objective QoS of high quality mobile VoIP voice telecommunication. For measuring the conversational quality, the VoIP telecommunication system is implemented in two smart phones connected with VoIP. The VoIP telecommunication system consists of echo cancellation, noise reduction, speech encoding/decoding, packet generation with RTP (Real-Time Protocol), jitter buffer control and POS (Play-out Schedule) with LC (loss Concealment). The CQM system is connected to a microphone and a speaker of each smart phone. The voice signal of each speaker is recorded and used to measure CE (Conversational Efficiency), CS (Conversational Symmetry), PESQ (Perceptual Evaluation of Speech Quality) and CE-CS-PESQ correlation. We prove the CQM system by measuring CE, CS and PESQ under various SNR, delay and loss due to IP network environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.